RAM初始化的下板验证
本实验基于xilinx artix-7芯片验证实现，有时间有兴趣的朋友可在其他fpga芯片上实现验证。
当大家看到《xilinx verilog语法技巧(三)–ram的初始化》文章的时候很多人认为initial语句，$readmemb语句均是不可综合语句（只能用来写测试文件），但是xilinx的综合器已经悄然改变了这一点。
rams_init_file源码：
// initializing block ram from external data file// binary data// file: rams_init_file.vmodule rams_init_file (clk, we, addr, din, dout);input clk;input we;input [5:0] addr;input [31:0] din;output [31:0] dout;reg [31:0] ram [0:63];reg [31:0] dout;initial begin$readmemb(rams_init_file.data,ram);endalways @(posedge clk)begin if (we) ram[addr] <= din; dout <= ram[addr];end endmodule
rams_init_file.data源文件：
00001110110000011001111011000110001010110010110101010010001000110111010001010001100001110000111101000001010000100101001110010100000010011010011111111010001010110010110100101111111010101010011111101111000100111000111101101101100011110100100110010000111011110000000110001110001111001001111111011111001110101011111001001010111001110101001111101100110010101100010000100110110011110010100110001011100101011111111111100001111101011101100100000101101110100100101100000011100101011010111011100001111111001010111010011110011011110110100101000011011100010101010001101111100001100010010011110000111101101111001100001011101011010011110101001001000111000101110000101011111110111010111001011101000100100111010010110101111101110001000001010111011011011110011111000111101010110000110101110100000011101111111000011111000100111101011110001110010111010110111000111110001101010110111110111100000000010011101011011011110000010011010011011111000100000001111111001011011001111101010101100100100000011100100101110000100010000001001110110010100011111100100010001110100101000110000110000000100111010011100111100011110111110100101000101010100001111000000011011110100011111011101110110011010111101111000110011001000101111000010010101101110111001001110010111010111101101011001101010011101101010001110110011010011110110111000101010001010000011000100000011001011011100110101011101000001101010000111001010110111000111111000001111101011101010100101000000000111111110110111100100011000011001000000010001111100110001110101100010010111001001111111111101111010100010100011111000011000101000011100110100000011011010010111110101000111010011000011110110010100111001101011111010110100100101110110010100100010011111110011011010111110010111101100100110111011000010011011110110110110111100101110011100110100111001110010000101111110101100000000000101101111100101011001010100110011010000010001000011011110010101111110010011100011101010010000110001000011100010100100000111100101111110001101101111010110000100010100000000101001000011100000100011000110100010100111010010011010100010001100100100111
tb_rams_init_file测试顶层文件：
`timescale 1ns / 1psmodule tb_rams_init_file( input clk, input reset, output [2:0] led_rgb0, output [2:0] led_rgb1, output [2:0] led_rgb2, output [2:0] led_rgb3 );reg [5:0] addr;wire [31:0] dout;reg [27:0] cnt;assign led_rgb0 = dout[2:0];assign led_rgb1 = dout[5:3];assign led_rgb2 = dout[8:6];assign led_rgb3 = dout[11:9];always @(posedge clk ) begin if(reset==1'b1) begin cnt <= 28'd0; addr <= 0; end else if(cnt == 28'd100000000)begin//1s cnt <= 28'd0; addr <= addr +1; end else begin cnt <= cnt + 1; addr <= addr; endendrams_init_file u_rams_init_file( .clk(clk), .we(1'b0), .addr(addr), .din(32'b0), .dout(dout));endmodule
约束文件(根据自己板卡)：
set_property package_pin e3 [get_ports clk]set_property iostandard lvcmos33 [get_ports clk]set_property package_pin d9 [get_ports reset]set_property iostandard lvcmos33 [get_ports reset]set_property package_pin e1 [get_ports led_rgb0[0]]set_property iostandard lvcmos33 [get_ports led_rgb0[0]]set_property package_pin g6 [get_ports led_rgb0[1]]set_property iostandard lvcmos33 [get_ports led_rgb0[1]]set_property package_pin f6 [get_ports led_rgb0[2]]set_property iostandard lvcmos33 [get_ports led_rgb0[2]]set_property package_pin g4 [get_ports led_rgb1[0]]set_property iostandard lvcmos33 [get_ports led_rgb1[0]]set_property package_pin g3 [get_ports led_rgb1[1]]set_property iostandard lvcmos33 [get_ports led_rgb1[1]]set_property package_pin j4 [get_ports led_rgb1[2]]set_property iostandard lvcmos33 [get_ports led_rgb1[2]]set_property package_pin h4 [get_ports led_rgb2[0]]set_property iostandard lvcmos33 [get_ports led_rgb2[0]]set_property package_pin j3 [get_ports led_rgb2[1]]set_property iostandard lvcmos33 [get_ports led_rgb2[1]]set_property package_pin j2 [get_ports led_rgb2[2]]set_property iostandard lvcmos33 [get_ports led_rgb2[2]]set_property package_pin k2 [get_ports led_rgb3[0]]set_property iostandard lvcmos33 [get_ports led_rgb3[0]]set_property package_pin k1 [get_ports led_rgb3[1]]set_property iostandard lvcmos33 [get_ports led_rgb3[1]]set_property package_pin h6 [get_ports led_rgb3[2]]set_property iostandard lvcmos33 [get_ports led_rgb3[2]]
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当大家看到《xilinx verilog语法技巧(三)–ram的初始化》文章的时候很多人认为initial语句，$readmemb语句均是不可综合语句（只能用来写测试文件），但是xilinx的综合器已经悄然改变了这一点。
rams_init_file源码：
// initializing block ram from external data file// binary data// file: rams_init_file.vmodule rams_init_file (clk, we, addr, din, dout);input clk;input we;input [5:0] addr;input [31:0] din;output [31:0] dout;reg [31:0] ram [0:63];reg [31:0] dout;initial begin$readmemb(rams_init_file.data,ram);endalways @(posedge clk)begin if (we) ram[addr] <= din; dout <= ram[addr];end endmodule
rams_init_file.data源文件：
00001110110000011001111011000110001010110010110101010010001000110111010001010001100001110000111101000001010000100101001110010100000010011010011111111010001010110010110100101111111010101010011111101111000100111000111101101101100011110100100110010000111011110000000110001110001111001001111111011111001110101011111001001010111001110101001111101100110010101100010000100110110011110010100110001011100101011111111111100001111101011101100100000101101110100100101100000011100101011010111011100001111111001010111010011110011011110110100101000011011100010101010001101111100001100010010011110000111101101111001100001011101011010011110101001001000111000101110000101011111110111010111001011101000100100111010010110101111101110001000001010111011011011110011111000111101010110000110101110100000011101111111000011111000100111101011110001110010111010110111000111110001101010110111110111100000000010011101011011011110000010011010011011111000100000001111111001011011001111101010101100100100000011100100101110000100010000001001110110010100011111100100010001110100101000110000110000000100111010011100111100011110111110100101000101010100001111000000011011110100011111011101110110011010111101111000110011001000101111000010010101101110111001001110010111010111101101011001101010011101101010001110110011010011110110111000101010001010000011000100000011001011011100110101011101000001101010000111001010110111000111111000001111101011101010100101000000000111111110110111100100011000011001000000010001111100110001110101100010010111001001111111111101111010100010100011111000011000101000011100110100000011011010010111110101000111010011000011110110010100111001101011111010110100100101110110010100100010011111110011011010111110010111101100100110111011000010011011110110110110111100101110011100110100111001110010000101111110101100000000000101101111100101011001010100110011010000010001000011011110010101111110010011100011101010010000110001000011100010100100000111100101111110001101101111010110000100010100000000101001000011100000100011000110100010100111010010011010100010001100100100111
tb_rams_init_file测试顶层文件：
`timescale 1ns / 1psmodule tb_rams_init_file( input clk, input reset, output [2:0] led_rgb0, output [2:0] led_rgb1, output [2:0] led_rgb2, output [2:0] led_rgb3 );reg [5:0] addr;wire [31:0] dout;reg [27:0] cnt;assign led_rgb0 = dout[2:0];assign led_rgb1 = dout[5:3];assign led_rgb2 = dout[8:6];assign led_rgb3 = dout[11:9];always @(posedge clk ) begin if(reset==1'b1) begin cnt <= 28'd0; addr <= 0; end else if(cnt == 28'd100000000)begin//1s cnt <= 28'd0; addr <= addr +1; end else begin cnt <= cnt + 1; addr <= addr; endendrams_init_file u_rams_init_file( .clk(clk), .we(1'b0), .addr(addr), .din(32'b0), .dout(dout));endmodule
约束文件(根据自己板卡)：
set_property package_pin e3 [get_ports clk]set_property iostandard lvcmos33 [get_ports clk]set_property package_pin d9 [get_ports reset]set_property iostandard lvcmos33 [get_ports reset]set_property package_pin e1 [get_ports led_rgb0[0]]set_property iostandard lvcmos33 [get_ports led_rgb0[0]]set_property package_pin g6 [get_ports led_rgb0[1]]set_property iostandard lvcmos33 [get_ports led_rgb0[1]]set_property package_pin f6 [get_ports led_rgb0[2]]set_property iostandard lvcmos33 [get_ports led_rgb0[2]]set_property package_pin g4 [get_ports led_rgb1[0]]set_property iostandard lvcmos33 [get_ports led_rgb1[0]]set_property package_pin g3 [get_ports led_rgb1[1]]set_property iostandard lvcmos33 [get_ports led_rgb1[1]]set_property package_pin j4 [get_ports led_rgb1[2]]set_property iostandard lvcmos33 [get_ports led_rgb1[2]]set_property package_pin h4 [get_ports led_rgb2[0]]set_property iostandard lvcmos33 [get_ports led_rgb2[0]]set_property package_pin j3 [get_ports led_rgb2[1]]set_property iostandard lvcmos33 [get_ports led_rgb2[1]]set_property package_pin j2 [get_ports led_rgb2[2]]set_property iostandard lvcmos33 [get_ports led_rgb2[2]]set_property package_pin k2 [get_ports led_rgb3[0]]set_property iostandard lvcmos33 [get_ports led_rgb3[0]]set_property package_pin k1 [get_ports led_rgb3[1]]set_property iostandard lvcmos33 [get_ports led_rgb3[1]]set_property package_pin h6 [get_ports led_rgb3[2]]set_property iostandard lvcmos33 [get_ports led_rgb3[2]]
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