MAX19517双通道、10位、130Msps ADC
the max19517 dual-channel, analog-to-digital converter (adc) provides 10-bit resolution and a maximum sample rate of 130msps.
the max19517 analog input accepts a wide 0.4v to 1.4v input common-mode voltage range, allowing dc-coupled inputs for a wide range of rf, if, and baseband front-end components. the max19517 provides excellent dynamic performance from baseband to high input frequencies beyond 400mhz, making the device ideal for zero-intermediate frequency (zif) and highintermediate frequency (if) sampling applications. the typical signal-to-noise ratio (snr) performance is 59.8dbfs and typical spurious-free dynamic range (sfdr) is 82dbc at fin = 70mhz and fclk = 130mhz.
the max19517 operates from a 1.8v supply. additionally, an integrated, self-sensing voltage regulator allows operation from a 2.5v to 3.3v supply (avdd). the digital output drivers operate on an independent supply voltage (ovdd) over the 1.8v to 3.5v range. the analog power consumption is only 74mw per channel at vavdd = 1.8v. in addition to low operating power, the max19517 consumes only 1mw in power-down mode and 21mw in standby mode.
various adjustments and feature selections are available through programmable registers that are accessed through the 3-wire serial-port interface. alternatively, the serial-port interface can be disabled, with the three pins available to select output mode, data format, and clock-divider mode. data outputs are available through a dual parallel cmos-compatible output data bus that can also be configured as a single multiplexed parallel cmos bus.
the max19517 is available in a small 7mm x 7mm 48-pin thin qfn package and is specified over the -40°c to +85°c extended temperature range.
refer to the max19505, max19506, and max19507 data sheets for pin- and feature-compatible 8-bit, 65msps, 100msps, and 130msps versions, respectively. refer to the max19515 and max19516 data sheets for pin- and feature-compatible 10-bit, 65msps and 100msps versions, respectively.
关键特性
very-low-power operation (74mw/channel at 130msps) 1.8v or 2.5v to 3.3v analog supply excellent dynamic performance 59.8dbfs snr at 70mhz 82dbc sfdr at 70mhz user-programmable adjustments and feature selection through an spi™ interface selectable data bus (dual cmos or single multiplexed cmos) dclk output and programmable data output timing simplifies high-speed digital interface very wide input common-mode voltage range (0.4v to 1.4v) very high analog input bandwidth (> 850mhz) single-ended or differential analog inputs single-ended or differential clock input divide-by-one (div1), divide-by-two (div2), and divide-by-four (div4) clock modes two's complement, gray code, and offset binary output data format out-of-range indicator (dor) cmos output internal termination options (programmable) reversible bit order (programmable) data output test patterns small 7mm x 7mm 48-pin thin qfn package with exposed pad 应用/使用
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the max19517 analog input accepts a wide 0.4v to 1.4v input common-mode voltage range, allowing dc-coupled inputs for a wide range of rf, if, and baseband front-end components. the max19517 provides excellent dynamic performance from baseband to high input frequencies beyond 400mhz, making the device ideal for zero-intermediate frequency (zif) and highintermediate frequency (if) sampling applications. the typical signal-to-noise ratio (snr) performance is 59.8dbfs and typical spurious-free dynamic range (sfdr) is 82dbc at fin = 70mhz and fclk = 130mhz.
the max19517 operates from a 1.8v supply. additionally, an integrated, self-sensing voltage regulator allows operation from a 2.5v to 3.3v supply (avdd). the digital output drivers operate on an independent supply voltage (ovdd) over the 1.8v to 3.5v range. the analog power consumption is only 74mw per channel at vavdd = 1.8v. in addition to low operating power, the max19517 consumes only 1mw in power-down mode and 21mw in standby mode.
various adjustments and feature selections are available through programmable registers that are accessed through the 3-wire serial-port interface. alternatively, the serial-port interface can be disabled, with the three pins available to select output mode, data format, and clock-divider mode. data outputs are available through a dual parallel cmos-compatible output data bus that can also be configured as a single multiplexed parallel cmos bus.
the max19517 is available in a small 7mm x 7mm 48-pin thin qfn package and is specified over the -40°c to +85°c extended temperature range.
refer to the max19505, max19506, and max19507 data sheets for pin- and feature-compatible 8-bit, 65msps, 100msps, and 130msps versions, respectively. refer to the max19515 and max19516 data sheets for pin- and feature-compatible 10-bit, 65msps and 100msps versions, respectively.
关键特性
very-low-power operation (74mw/channel at 130msps) 1.8v or 2.5v to 3.3v analog supply excellent dynamic performance 59.8dbfs snr at 70mhz 82dbc sfdr at 70mhz user-programmable adjustments and feature selection through an spi™ interface selectable data bus (dual cmos or single multiplexed cmos) dclk output and programmable data output timing simplifies high-speed digital interface very wide input common-mode voltage range (0.4v to 1.4v) very high analog input bandwidth (> 850mhz) single-ended or differential analog inputs single-ended or differential clock input divide-by-one (div1), divide-by-two (div2), and divide-by-four (div4) clock modes two's complement, gray code, and offset binary output data format out-of-range indicator (dor) cmos output internal termination options (programmable) reversible bit order (programmable) data output test patterns small 7mm x 7mm 48-pin thin qfn package with exposed pad 应用/使用
数字机顶盒
if和基带通信，包括：蜂窝基站及点对点微波接收机
便携式仪表和低功耗数据采集
超声和医学成像
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摩尔的极限——基于单元原子半导体的固态量子计算设备
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