分析ADC系统失真所造成源电阻-Analysis of AD
abstract: analog-to-digital converter (adc) data sheets and application typically recommend driving their inputs with a low source impedance. this application note explains the possible effects such as increased gain error and distortion when using high impedance to drive an adc without a buffer.
analog-to-digital converter (adc) users have been instructed by endless data sheets and application notes to drive their adcs with a low source impedance. however, these instructions often do not tell us what can happen if a low impedance is not used and what effects it can have on circuit performance. this article explains the principles behind and techniques for understanding the source of the distortion caused from a high source resistance on the input to an analog-to-digital converter.
we can begin to understand the problem of high-source impedance effects by looking at the simple circuit below in figure 1. it addresses a common need to scale a ±10v signal to a 0 to 5v adc input with a simple voltage divider.
figure 1. scaling adc input with a simple voltage divider.
for this circuit, the effective driving impedance into the adc is the thevenin equivalent impedance seen looking back into the divider, which equals the parallel combination of the divider resistors. this finite input resistance acts as a voltage divider with the input impedance of the adc causing a low-frequency gain error as shown in figure 2.
figure 2. error current and voltage due to finite input impedance.
in addition to the gain error, there are two other problems caused by this finite input resistance. the first is a settling time error. this is caused by the fact that the sampling capacitor is only allowed to charge for part of the sampling cycle, referred to the acquisition period. during this acquisition period the settling time will be increased due the additional time constant created by the input resistance and the input sampling capacitance. this error can be estimated by looking at the settling of a rc time constant using the input capacitance and the source impedance over the acquisition time period using the following equation: ratio of settling = 1-e-(tacquisition/rc) this is mostly a linear error, but can have some non-linear components.
the second error, which can sometimes be more critical than the gain errors discussed above, is distortion. the cause of this distortion can be understood by realizing that the input resistance and input capacitance of the adc create a low-pass filter with a frequency dependant gain error. the distortion occurs due to the normal voltage dependant characteristic of the capacitor, meaning that the capacitance changes with the voltage applied. this characgteristic can be more pronounced in semiconductor process technology.
an equation that describes this change in one region of the voltage curve is: c = c0 × ( 1 + k × v- ), where
c0 is the nominal capacitance,
v is the voltage across the capacitance,
k is a semiconductor process and design dependant constant.
a plot of a typical curve of this capacitance¹ is shown in figure 3.
figure 3. variation of a capacitor with applied voltage.
referring back to figure 2, this voltage-dependant capacitance causes the current necessary to charge the capacitance to vary with voltage (in addition to frequency). this current travels through the adc driving impedance, which creates a voltage drop error, which again varies with voltage. if this error were independent of voltage, it would create a linear error, as discussed above. however, since it is voltage dependant, it creates a non-linear error. for a sine wave, this error contains harmonics. and, since this error originates as a current charging a capacitance, the error is non-existant at dc, and gets proportionately larger with frequency.
an example of the order of magnitude of this error for one adc is that at 500khz input frequency, 1kω source impedance, and full-scale input voltage yields a 70db thd. this distortion component will approximately vary linearly with both impedance and frequency. for example, input frequencies and source impedance combinations of both (5mhz, 1kω) and (500khz, 10kω) will be 10x or 20db worse, yielding 50db thd. note, since this effect is highly dependant on both the design and semiconductor process, different adcs can have radically different numbers. hence, these numbers should not be applied towards any design.
there is no easy way to determine how much of a problem this is for your circuit because semiconductor manufacturers don't specify parameters like voltage-dependant input capacitance. the best advice is to follow the manufacturers recommendation for the maximum size of the input resistance required to meet the stated performance. it is always a good practice to always drive the input of the adc with as low of an impedance as possible.
a better solution is to use the ic products that incorporate the above resistive divider on the ic. for these products, the effects of the source impedance has been accounted for, and/or compensated for by the ic design engineers to make sure the part meets its distortion specifications.
examples of parts that have been pre-engineered for you to translate the higher input voltage onto an internal lower voltage include the max1159, max1189, max1132-35, and max1142-45. these converters have a variety of power voltages, and input voltages, and resolution (# of bits), as shown in the table 1 below.
table 1. list of adcs from maxim with input range beyond the voltage rails
part input voltage range software
selectable
input range power rail resolution sample rate
(ksps) interface
max 1132 0 .. 12v, ±12v yes 5v 16 200 spi- serial
max 1133 0 .. 4v, ±4v yes 5v 16 200 spi- serial
max 1134 0 .. 6v, ± 6v yes 3.3v 16 150 spi- serial
max 1135 0 .. 2v, ± 2v yes 3.3v 16 150 spi- serial
max 1142 0 .. 12v, ±12v yes 5v 14 200 spi- serial
max 1143 0 .. 4v, ±4v yes 5v 14 200 spi- serial
max 1144 0 .. 6v, ± 6v yes 3.3v 14 150 spi- serial
max 1145 0 .. 2v, ± 2v yes 3.3v 14 150 spi- serial
max 1157 0 .. 10v no 5v, 2.7..5.25 dout 14 135 spi – serial
max 1159 ± 10v no 5v, 2.7..5.25 dout 14 135 spi – serial
max 1175 ± 5v no 5v, 2.7..5.25 dout 14 135 spi – serial
max 1179 ±5v no 5v, 2.7..5.25 dout 16 135 spi – serial
max 1187 0 .. 10v no 5v, 2.7..5.25 dout 16 135 spi – serial
max 1189 ± 10v no 5v, 2.7..5.25 dout 16 135 spi – serial
max1270 ±10v, ±5v, 0..10v, 0..5v yes 5v 12 110 spi – serial
max1271 ± vref, ± vref / 2, 0.. vref, 0..vref / 2 yes 5v 12 110 spi- serial
max127 ±10v, ±5v, 0..10v, 0..5v yes 5v 12 8 i2c – serial
max128 ± vref, ± vref / 2, 0.. vref, 0..vref / 2 yes 5v 12 8 i2c – serial
max 196, max 197 ±10v, ±5v, 0..10v, 0..5v yes 5v 12 100 parallel
max 198, max 199 ± vref, ± vref / 2, 0.. vref, 0..vref / 2 yes 5v 12 100 parallel
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analog-to-digital converter (adc) users have been instructed by endless data sheets and application notes to drive their adcs with a low source impedance. however, these instructions often do not tell us what can happen if a low impedance is not used and what effects it can have on circuit performance. this article explains the principles behind and techniques for understanding the source of the distortion caused from a high source resistance on the input to an analog-to-digital converter.
we can begin to understand the problem of high-source impedance effects by looking at the simple circuit below in figure 1. it addresses a common need to scale a ±10v signal to a 0 to 5v adc input with a simple voltage divider.
figure 1. scaling adc input with a simple voltage divider.
for this circuit, the effective driving impedance into the adc is the thevenin equivalent impedance seen looking back into the divider, which equals the parallel combination of the divider resistors. this finite input resistance acts as a voltage divider with the input impedance of the adc causing a low-frequency gain error as shown in figure 2.
figure 2. error current and voltage due to finite input impedance.
in addition to the gain error, there are two other problems caused by this finite input resistance. the first is a settling time error. this is caused by the fact that the sampling capacitor is only allowed to charge for part of the sampling cycle, referred to the acquisition period. during this acquisition period the settling time will be increased due the additional time constant created by the input resistance and the input sampling capacitance. this error can be estimated by looking at the settling of a rc time constant using the input capacitance and the source impedance over the acquisition time period using the following equation: ratio of settling = 1-e-(tacquisition/rc) this is mostly a linear error, but can have some non-linear components.
the second error, which can sometimes be more critical than the gain errors discussed above, is distortion. the cause of this distortion can be understood by realizing that the input resistance and input capacitance of the adc create a low-pass filter with a frequency dependant gain error. the distortion occurs due to the normal voltage dependant characteristic of the capacitor, meaning that the capacitance changes with the voltage applied. this characgteristic can be more pronounced in semiconductor process technology.
an equation that describes this change in one region of the voltage curve is: c = c0 × ( 1 + k × v- ), where
c0 is the nominal capacitance,
v is the voltage across the capacitance,
k is a semiconductor process and design dependant constant.
a plot of a typical curve of this capacitance¹ is shown in figure 3.
figure 3. variation of a capacitor with applied voltage.
referring back to figure 2, this voltage-dependant capacitance causes the current necessary to charge the capacitance to vary with voltage (in addition to frequency). this current travels through the adc driving impedance, which creates a voltage drop error, which again varies with voltage. if this error were independent of voltage, it would create a linear error, as discussed above. however, since it is voltage dependant, it creates a non-linear error. for a sine wave, this error contains harmonics. and, since this error originates as a current charging a capacitance, the error is non-existant at dc, and gets proportionately larger with frequency.
an example of the order of magnitude of this error for one adc is that at 500khz input frequency, 1kω source impedance, and full-scale input voltage yields a 70db thd. this distortion component will approximately vary linearly with both impedance and frequency. for example, input frequencies and source impedance combinations of both (5mhz, 1kω) and (500khz, 10kω) will be 10x or 20db worse, yielding 50db thd. note, since this effect is highly dependant on both the design and semiconductor process, different adcs can have radically different numbers. hence, these numbers should not be applied towards any design.
there is no easy way to determine how much of a problem this is for your circuit because semiconductor manufacturers don't specify parameters like voltage-dependant input capacitance. the best advice is to follow the manufacturers recommendation for the maximum size of the input resistance required to meet the stated performance. it is always a good practice to always drive the input of the adc with as low of an impedance as possible.
a better solution is to use the ic products that incorporate the above resistive divider on the ic. for these products, the effects of the source impedance has been accounted for, and/or compensated for by the ic design engineers to make sure the part meets its distortion specifications.
examples of parts that have been pre-engineered for you to translate the higher input voltage onto an internal lower voltage include the max1159, max1189, max1132-35, and max1142-45. these converters have a variety of power voltages, and input voltages, and resolution (# of bits), as shown in the table 1 below.
table 1. list of adcs from maxim with input range beyond the voltage rails
part input voltage range software
selectable
input range power rail resolution sample rate
(ksps) interface
max 1132 0 .. 12v, ±12v yes 5v 16 200 spi- serial
max 1133 0 .. 4v, ±4v yes 5v 16 200 spi- serial
max 1134 0 .. 6v, ± 6v yes 3.3v 16 150 spi- serial
max 1135 0 .. 2v, ± 2v yes 3.3v 16 150 spi- serial
max 1142 0 .. 12v, ±12v yes 5v 14 200 spi- serial
max 1143 0 .. 4v, ±4v yes 5v 14 200 spi- serial
max 1144 0 .. 6v, ± 6v yes 3.3v 14 150 spi- serial
max 1145 0 .. 2v, ± 2v yes 3.3v 14 150 spi- serial
max 1157 0 .. 10v no 5v, 2.7..5.25 dout 14 135 spi – serial
max 1159 ± 10v no 5v, 2.7..5.25 dout 14 135 spi – serial
max 1175 ± 5v no 5v, 2.7..5.25 dout 14 135 spi – serial
max 1179 ±5v no 5v, 2.7..5.25 dout 16 135 spi – serial
max 1187 0 .. 10v no 5v, 2.7..5.25 dout 16 135 spi – serial
max 1189 ± 10v no 5v, 2.7..5.25 dout 16 135 spi – serial
max1270 ±10v, ±5v, 0..10v, 0..5v yes 5v 12 110 spi – serial
max1271 ± vref, ± vref / 2, 0.. vref, 0..vref / 2 yes 5v 12 110 spi- serial
max127 ±10v, ±5v, 0..10v, 0..5v yes 5v 12 8 i2c – serial
max128 ± vref, ± vref / 2, 0.. vref, 0..vref / 2 yes 5v 12 8 i2c – serial
max 196, max 197 ±10v, ±5v, 0..10v, 0..5v yes 5v 12 100 parallel
max 198, max 199 ± vref, ± vref / 2, 0.. vref, 0..vref / 2 yes 5v 12 100 parallel
LFPAK系列全新8*8封装提升功率效率
高通公布最新财报 营收同比大涨63%
浅谈智慧农业云平台
嵌入式多参数监护仪设计
解读关于STM32问题集之BOOT0和BOOT1的作用
分析ADC系统失真所造成源电阻-Analysis of AD
电磁波的模式有什么类型
TensorFlow Community Spotlight获奖项目
应用材料公司发布2022财年第四季度及全年财务报告
三年保修液晶屏电视一览(有质保才安心)
苹果手机最快将会在2020年全面转用OLED屏幕
寒武纪正式对外公布其首颗AI训练芯片思元290及玄思1000智能加速器
自动驾驶的耳目知多少：激光雷达篇
千元机的配置做的足够好了，但屏幕上确都不怎么在意
双11年轻人买啥冰箱？看完海尔智家Leader再决定
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编码不是万能钥匙，扫码制度背后问题多
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智能极简园区网络解决方案重构企业园区网络
Lumex推出彩色LED指示器应用的理想选择