Interfacing the MAX7651/MAX765
abstract: this article covers the specific hardware description and software routines required to interface the max7651 and max7652 12-bit data acquisition system to the 24c02 2-wire serial eeprom. detailed software code is provided. since the max7651/52 is based on a standard 8051 processor core the information presented here is useful to any standard 8051-based design.
the 24cxx series of 2-wire serial eeproms are widely used in 8051 microprocessor systems. although the max7651/max7652 flash-programmable 12-bit data acquisition systems have 16k of internal flash memory, there are many legacy products that use small and inexpensive external memories.
this application note provides basic 2-wire write and read software subroutines. they can be easily modified to address additional features of eeproms, such as memory protection and bank addressing.
there are many derivatives of the 24c02 serial eeprom, which include additional memory and page addressing. the 24c02 is widely used and is the part used in this example. other derivative parts can use this code with minor modifications. eeprom signals and timingthe 24cxx family uses two i/o lines for interfacing: scl (serial clock) and sda (serial data). scl edges have different functions, depending on whether a device is being read from or written to. when clocking data into the device, the positive edges of the clock latch the data. the negative clock edges clock data out of the device.
the sda signal is bi-directional, and is physically an open-drain so that multiple eeproms or other devices can share the pin. both scl and sda must be pulled high externally.
the protocol used by the eeprom is based in part on an ack (acknowledge) bit sent by the eeprom, if the data sent to it has been received. all addresses and data are sent in 8-bit words. the eeprom sends the ack as a low bit period during the ninth clock cycle. the eeprom looks for specific transitions on the scl and sda pins to qualify read and write.
data on the sda pin may change only during the time scl is low. data changes during scl high periods indicate a start or stop condition. a start condition is a high-to-low transition of sda with scl high. all data transfers must begin with a start condition.
a stop condition is a low-to-high transition of sda with scl high. all data transfers must end with a stop condition. after a read, the stop places the eeprom in a standby power mode. refer to figure 1 for start and stop conditions.
figure 1. start and stop conditions. device addressingthe 24c02 has 3 physical pins, designated a2, a1, and a0, which are tied to logic 1 or 0 levels. this allows eight unique hardware addresses, so that up to eight 24c02s can share the scl and sda lines without conflict. there is an internal address comparator that looks for a match between the address sent by the master controller and the 24c02's unique 7-bit address, determined in part by a2, a1, and a0. refer to table 1below.
table 1. 24c02 device address
msb lsb
1 0 1
0
a2
a1
a0
r/~w
the device address is sent immediately after a start condition. the first four bits are the sequence 1010, which is a simple noise filter which prevents a random noise burst on the lines from accessing the device. the last bit sent is a 1 for read and a 0 for write. the code example below is for random read/write operations. the part can also perform page write/sequential read with slight code modifications. see the 24c02 data sheet for more information. byte write to memorythe byte write sequence is shown in figure 2. after receiving a start condition and a device address, the eeprom sends an ack if the device address matches its own unique address. the max7651 waits for the ack and aborts communication if it is not present. next, an 8-bit byte address is sent, followed by another ack. the max7651 then sends the 8-bit data byte, waits for the third ack, and sends a stop condition.
figure 2. write operation.
it is important to note that after the stop condition is received, the eeprom internally waits for the data to be stored into its internal memory array. this can take as long as 10ms. the 24c02 will ignore attempted accesses while the internal eeprom is being programmed. the part can be polled for completion of the internal write cycle. this involves sending another start condition (also called a repeated start), followed by the device address byte. note, in this case, there is no stop condition sent. the eeprom will send an ack if the internal programming cycle is completed. the max7651 can also be programmed to wait 10ms before proceeding. byte read from memoryreading a byte from the 24c02 eeprom at a random address requires that a dummy write operation be performed before the read. see figure 3.
the sequence is: start condition
send device address with r/~w = 0 'dummy write' command
wait for ack
send byte memory address
wait for ack
send repeated start condition
send device address with r/~w = 1 (read command)
wait for ack
read the 8 data bits into the max7651, msb first
no ack
stop condition this sequence is quite involved! the total number of scl transitions required for a read is 38.
figure 3. read operation. code examplethe following assembly language code example assumes a 24c02 eeprom addressed at device 0h (i.e., a2 = a1 = a0 = ground). the max7651 uses two unused general-purpose i/o port pins to bit-bang the serial clock (scl) and the bi-direction data line (sda). two internal ram locations are needed: ee_addr stores the byte address and ee_data stores the data.
; eeprom routines for the 24c02, with a2 = a1 = a0 = 0
ee_write: call ee_start ; send a start flag to the eeprom
mov a,#0a0h ; specify a write eeprom @ address 0h
call shout ; shift out the device address
jc wr_abort ; abort if no ack from eeprom
mov a,ee_addr ; get eeprom memory address
call shout ; shift out the memory address
jc wr_abort ; abort if no ack from eeprom
mov a, ee_data ; get the data to be written
call shout ; shift out the data
jc wr_abort ;
clr c ;
wr_abort: call ee_stop ; send stop condition to eeprom
; wait for write time of the 24c02 {10ms}
; the eeprom takes 10ms to internally store the data. you can either
; put the microcontroller in a wait state, or continue with execution,
; keeping in mind that the eeprom data is not stored for 10ms!
ret ; go back to main program
; read the eeprom data - first perform 'dummy write'
ee_read: mov ee_data,#00h ; clear old data
call ee_start ; send a start flag to eeprom
mov a,#0a0h ; specify a write to eeprom @ address 0h
call shout ; perform 'dummy write'
jc rd_abort ; abort if no ack
mov a,ee_addr ; load eeprom memory location
; from which to read
call shout ; write eeprom memory location
jc rd_abort ; abort if no ack
; now read the data!
ee_write: call ee_start ; send a start flag
mov a,#0a1h ; specify a read from eeprom
call shout ; shift out eeprom address
jc rd_abort ; abort if no ack
call shin ; shift in the data from eeprom
mov ee_data,a ; store the data
call nak ; send a nak (no acknowledge) to the
; eeprom
clr c ; clear error flag
rd_abort: call ee_stop ; all done
ret ;
; ee_start bit-bangs a start sequence to eeprom (hi-to-low sda transition
; with scl high).
ee_start: setb sda
setb scl ; set both bits
nop ; delay
clr sda ; start condition; sda hi to low transition
nop
nop ; eeprom access time delay
clr scl
clr c ; clear error flag
ret ; all done
; ee_stop sends a stop sequence to the eeprom (low-to-high sda transition
; with scl high).
ee_stop: clr sda
nop
nop
setb scl
nop
nop ; setup time delay
setb sda ; send a stop condition
ret
; shout shifts data out to the eeprom
shout: push b
mov b,#8 ; save b and load bit count
eeout: rlc a ; shift bit left (rlc=rotate left through
; carry)
mov sda,c ; get data bit from carry
nop
setb scl ; clock in 1-bit
nop ; clock high time
clr scl ; clock is now low
djnz b,eeout ; do it 8 times
setb sda ; release sda for ack
nop
nop
setb scl ; ack clock
nop
mov c,sda ; get the ack
clr scl ; clear the clock bit
pop b ; restore whatever b was
ret
; shin shift data in from the eeprom
shin: setb sda ; make sda an input
push b
mov b,#8 ; save b and set bit counter
eein: nop
setb scl ; set clock
nop
nop ; eeprom access time
setb sda ; set = 1 so used as input
mov c,sda ; read 1-bit
rlc a ; shift bit left
clr scl ; clear clock bit
djnz b,eein ; get next bit if less than 8 bits read
pop b
ret
; ack sends an eeprom acknowldege
ack: clr sda
nop
nop
setb scl ; clock the ack
nop
clr scl ; bring clock low
ret
; nak sends a no acknowledge
nak: setb sda
nop
nop
setb scl ; clock the nak
nop
clr scl ; bring clock low
ret
$eject
不同低通滤波器的增益大小案例公式和电路曲线
千兆光模块还能满足现代网络需求吗？
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Interfacing the MAX7651/MAX765
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为什么Eplan经过培训以后依然很难用起来
the 24cxx series of 2-wire serial eeproms are widely used in 8051 microprocessor systems. although the max7651/max7652 flash-programmable 12-bit data acquisition systems have 16k of internal flash memory, there are many legacy products that use small and inexpensive external memories.
this application note provides basic 2-wire write and read software subroutines. they can be easily modified to address additional features of eeproms, such as memory protection and bank addressing.
there are many derivatives of the 24c02 serial eeprom, which include additional memory and page addressing. the 24c02 is widely used and is the part used in this example. other derivative parts can use this code with minor modifications. eeprom signals and timingthe 24cxx family uses two i/o lines for interfacing: scl (serial clock) and sda (serial data). scl edges have different functions, depending on whether a device is being read from or written to. when clocking data into the device, the positive edges of the clock latch the data. the negative clock edges clock data out of the device.
the sda signal is bi-directional, and is physically an open-drain so that multiple eeproms or other devices can share the pin. both scl and sda must be pulled high externally.
the protocol used by the eeprom is based in part on an ack (acknowledge) bit sent by the eeprom, if the data sent to it has been received. all addresses and data are sent in 8-bit words. the eeprom sends the ack as a low bit period during the ninth clock cycle. the eeprom looks for specific transitions on the scl and sda pins to qualify read and write.
data on the sda pin may change only during the time scl is low. data changes during scl high periods indicate a start or stop condition. a start condition is a high-to-low transition of sda with scl high. all data transfers must begin with a start condition.
a stop condition is a low-to-high transition of sda with scl high. all data transfers must end with a stop condition. after a read, the stop places the eeprom in a standby power mode. refer to figure 1 for start and stop conditions.
figure 1. start and stop conditions. device addressingthe 24c02 has 3 physical pins, designated a2, a1, and a0, which are tied to logic 1 or 0 levels. this allows eight unique hardware addresses, so that up to eight 24c02s can share the scl and sda lines without conflict. there is an internal address comparator that looks for a match between the address sent by the master controller and the 24c02's unique 7-bit address, determined in part by a2, a1, and a0. refer to table 1below.
table 1. 24c02 device address
msb lsb
1 0 1
0
a2
a1
a0
r/~w
the device address is sent immediately after a start condition. the first four bits are the sequence 1010, which is a simple noise filter which prevents a random noise burst on the lines from accessing the device. the last bit sent is a 1 for read and a 0 for write. the code example below is for random read/write operations. the part can also perform page write/sequential read with slight code modifications. see the 24c02 data sheet for more information. byte write to memorythe byte write sequence is shown in figure 2. after receiving a start condition and a device address, the eeprom sends an ack if the device address matches its own unique address. the max7651 waits for the ack and aborts communication if it is not present. next, an 8-bit byte address is sent, followed by another ack. the max7651 then sends the 8-bit data byte, waits for the third ack, and sends a stop condition.
figure 2. write operation.
it is important to note that after the stop condition is received, the eeprom internally waits for the data to be stored into its internal memory array. this can take as long as 10ms. the 24c02 will ignore attempted accesses while the internal eeprom is being programmed. the part can be polled for completion of the internal write cycle. this involves sending another start condition (also called a repeated start), followed by the device address byte. note, in this case, there is no stop condition sent. the eeprom will send an ack if the internal programming cycle is completed. the max7651 can also be programmed to wait 10ms before proceeding. byte read from memoryreading a byte from the 24c02 eeprom at a random address requires that a dummy write operation be performed before the read. see figure 3.
the sequence is: start condition
send device address with r/~w = 0 'dummy write' command
wait for ack
send byte memory address
wait for ack
send repeated start condition
send device address with r/~w = 1 (read command)
wait for ack
read the 8 data bits into the max7651, msb first
no ack
stop condition this sequence is quite involved! the total number of scl transitions required for a read is 38.
figure 3. read operation. code examplethe following assembly language code example assumes a 24c02 eeprom addressed at device 0h (i.e., a2 = a1 = a0 = ground). the max7651 uses two unused general-purpose i/o port pins to bit-bang the serial clock (scl) and the bi-direction data line (sda). two internal ram locations are needed: ee_addr stores the byte address and ee_data stores the data.
; eeprom routines for the 24c02, with a2 = a1 = a0 = 0
ee_write: call ee_start ; send a start flag to the eeprom
mov a,#0a0h ; specify a write eeprom @ address 0h
call shout ; shift out the device address
jc wr_abort ; abort if no ack from eeprom
mov a,ee_addr ; get eeprom memory address
call shout ; shift out the memory address
jc wr_abort ; abort if no ack from eeprom
mov a, ee_data ; get the data to be written
call shout ; shift out the data
jc wr_abort ;
clr c ;
wr_abort: call ee_stop ; send stop condition to eeprom
; wait for write time of the 24c02 {10ms}
; the eeprom takes 10ms to internally store the data. you can either
; put the microcontroller in a wait state, or continue with execution,
; keeping in mind that the eeprom data is not stored for 10ms!
ret ; go back to main program
; read the eeprom data - first perform 'dummy write'
ee_read: mov ee_data,#00h ; clear old data
call ee_start ; send a start flag to eeprom
mov a,#0a0h ; specify a write to eeprom @ address 0h
call shout ; perform 'dummy write'
jc rd_abort ; abort if no ack
mov a,ee_addr ; load eeprom memory location
; from which to read
call shout ; write eeprom memory location
jc rd_abort ; abort if no ack
; now read the data!
ee_write: call ee_start ; send a start flag
mov a,#0a1h ; specify a read from eeprom
call shout ; shift out eeprom address
jc rd_abort ; abort if no ack
call shin ; shift in the data from eeprom
mov ee_data,a ; store the data
call nak ; send a nak (no acknowledge) to the
; eeprom
clr c ; clear error flag
rd_abort: call ee_stop ; all done
ret ;
; ee_start bit-bangs a start sequence to eeprom (hi-to-low sda transition
; with scl high).
ee_start: setb sda
setb scl ; set both bits
nop ; delay
clr sda ; start condition; sda hi to low transition
nop
nop ; eeprom access time delay
clr scl
clr c ; clear error flag
ret ; all done
; ee_stop sends a stop sequence to the eeprom (low-to-high sda transition
; with scl high).
ee_stop: clr sda
nop
nop
setb scl
nop
nop ; setup time delay
setb sda ; send a stop condition
ret
; shout shifts data out to the eeprom
shout: push b
mov b,#8 ; save b and load bit count
eeout: rlc a ; shift bit left (rlc=rotate left through
; carry)
mov sda,c ; get data bit from carry
nop
setb scl ; clock in 1-bit
nop ; clock high time
clr scl ; clock is now low
djnz b,eeout ; do it 8 times
setb sda ; release sda for ack
nop
nop
setb scl ; ack clock
nop
mov c,sda ; get the ack
clr scl ; clear the clock bit
pop b ; restore whatever b was
ret
; shin shift data in from the eeprom
shin: setb sda ; make sda an input
push b
mov b,#8 ; save b and set bit counter
eein: nop
setb scl ; set clock
nop
nop ; eeprom access time
setb sda ; set = 1 so used as input
mov c,sda ; read 1-bit
rlc a ; shift bit left
clr scl ; clear clock bit
djnz b,eein ; get next bit if less than 8 bits read
pop b
ret
; ack sends an eeprom acknowldege
ack: clr sda
nop
nop
setb scl ; clock the ack
nop
clr scl ; bring clock low
ret
; nak sends a no acknowledge
nak: setb sda
nop
nop
setb scl ; clock the nak
nop
clr scl ; bring clock low
ret
$eject
不同低通滤波器的增益大小案例公式和电路曲线
千兆光模块还能满足现代网络需求吗？
动力电池pack技术发展现状及趋势分析
NVIDIA超级大核心曝光，拥有7552个流处理器
智慧环境监测系统中设备如何通过DTU接入ZWS云呢？
Interfacing the MAX7651/MAX765
上海新阳向上海硅产业转让上海新昇26.06%股权的交易已经完成
骁龙855支持5G吗
意华股份：增投东莞意博，拓宽投资范围
安科瑞Acrel-1000变电站综合自动化系统
采用MCU设计TWS耳机充电盒方案
Ultimaker以Ultimaker S5提高省事且专业的3D打印标准
美国商务部严禁美国公司直接向中国出口28nm相关的设备
医疗方案 | 基于FETMX6ULL-S实现的核酸自动提取仪
新款WALK-MAN人形机器人突破障碍物 成功打开干冰灭火器
博世汽车电子事业部原来是这样的？
低功耗蓝牙技术引领蓝牙码表革新
物联网将成为移动应用之后的下一个爆发点
端子与连接器的区别
为什么Eplan经过培训以后依然很难用起来