LX110T的板子上跑demo的时候遇到的一些错误的解决办法总结
.前一段时间在玩xilinx送我在跑xupv5-lx110t，首先跑xilinx给出的xupv5-lx110t的demo设计，结果发现遇到了一些错误但是自己在网上发现很少有答案，就把自己的一些总结贴出来：
（1）xupv5_bsb_std_ip时出现了问题，其错误描述如下：
[xupv5_bsb_system.ucf(1110)]: net xps_iic_0_gpo_pin not found. please
verify that:
1. the specified design element actually exists in the original design.
2. the specified object is spelled correctly in the constraint source file.
iostandard=lvcmos33;> [xupv5_bsb_system.ucf(1111)]: net xps_iic_0_gpo_pin
not found. please verify that:
1. the specified design element actually exists in the original design.
2. the specified object is spelled correctly in the constraint source file.
make: *** [__xps/xupv5_bsb_system_routed] error 1
解决办法：打开xupv5_bsb_std_ip文件夹里面的xupv5_bsb_system.mhs文件，
在其80行的位置，将port xps_iic_0_gpo_pin = xps_iic_0_gpo, dir = o, vec = [31:31]注释掉（即在前面加上#即可）或删除。
在其551行的位置，将 port gpo = xps_iic_0_gpo注释掉（即在前面加上#即可）或删除。
保存该文件。
然后打开xupv5_bsb_std_ip文件夹里面的xupv5_bsb_system.ucf文件
在其1110行和1111行的位置，将net xps_iic_0_gpo_pin loc=ak6; # dvi_reset_b
net xps_iic_0_gpo_pin iostandard=lvcmos33;两行删除或者注释掉。
保存该文件即可。
（2）.running drcs for oses, drivers and libraries ...
runnning drc for lwip library...
error:mdt - issued from tcl procedure ::sw_lwip_v3_00_a::lwip_drc line 12
lwip () - no ethernet mac cores are addressable from processor ppc440_0.
lwip requires atleast one emac (xps_ethernetlite | xps_ll_temac) core.
error:mdt - error while running drc for processor ppc440_0...
make: *** [ppc440_0/lib/libxil.a] error 2
done!
看到了这个问题，首先要学会自己找，上面明显提示是lwip出错，我们看一下datasheet就会发现： lwip provides an easy way to add tcp/ip-based networking capability to an embedded systemlwip_v3_00_a in edk provides adapters for the xps_ethernetlite and xps_ll_temac
xilinx? ethernet mac cores, and is based on the lwip stack version 1.2.0. this document
describes how to use lwip_v3_00_a to add networking capability to embedded software. 我们知道了它的作用，那就找吧，反正，xilinx里面是以mhs和mss文件为主线，那就行动吧
解决办法：在mss文件里找到# begin library
parameter library_name = lwip
parameter library_ver = 3.00.a
parameter proc_instance = microblaze_0
parameter api_mode = socket_api
end
将其注释掉或者删除。
（3）.error: failed to add write permission for
d:\..\microblaze_0\libsrc\lcd_ip_v1_00_a\
error:failed to copy
d:\..\drivers\lcd_ip_v1_00_a\src\ to
d:\..\microblaze_0\libsrc\lcd_ip_v1_00_a\
copying files for driver cpu_v1_11_b from
d:\xilinx\11.1\edk\sw\xilinxprocessoriplib\drivers\cpu_v1_11_b\src\ to
error: error while running copy files for processor microblaze_0...
make: *** [microblaze_0/lib/libxil.a] error 2
done!
解决办法：到桌面右键单击我的电脑，选择属性，再选择高级这一栏，单击环境变量，在新弹出的环境变量对话框下，单击系统变量的新建按钮，输入变量名：cygwin
在变量值中输入：nontsec，单击ok，重新启动xps，重新编译即可。
（4）.error:edk - d:\xilinx\sample\xupv5_bsb_std_ip\xupv5_bsb_system.mhs line 392 - parameter c_left_pos has value 7 which does not fall in the range (0:c_split-1), specified in mpd
error:edk - d:\xilinx\sample\xupv5_bsb_std_ip\xupv5_bsb_system.mhs line 393 - parameter c_split has value 31 which does not fall in the range (1:c_size_in-1), specified in mpd
error:edk - d:\xilinx\sample\xupv5_bsb_std_ip\xupv5_bsb_system.mhs line 392 - parameter c_left_pos has value 7 which does not fall in the range (0:c_split-1), specified in mpd
error:edk - d:\xilinx\sample\xupv5_bsb_std_ip\xupv5_bsb_system.mhs line 393 - parameter c_split has value 31 which does not fall in the range (1:c_size_in-1), specified in mpd
解决办法：this error can be safely ignored as it is being generated incorrectly. the project will implement.
官方给出的答复是忽略这个错误。
（5）.warning:edk:2099 - port:i_addrtag connector:ilmb_m_addrtag -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\microblaze_v7_20_a\data\mic
roblaze_v2_1_0.mpd line 232 - floating connection!
warning:edk:2099 - port:d_addrtag connector:dlmb_m_addrtag -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\microblaze_v7_20_a\data\mic
roblaze_v2_1_0.mpd line 273 - floating connection!
warning:edk:2099 - port:hostmiimsel connector:host_mii_sel -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\xps_ll_temac_v2_00_a\data\x
ps_ll_temac_v2_1_0.mpd line 264 - floating connection!
warning:edk:2099 - port:hostreq connector:host_req -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\xps_ll_temac_v2_00_a\data\x
ps_ll_temac_v2_1_0.mpd line 265 - floating connection!
warning:edk:2099 - port:hostaddr connector:host_addr -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\xps_ll_temac_v2_00_a\data\x
ps_ll_temac_v2_1_0.mpd line 266 - floating connection!
warning:edk:2099 - port:hostemac1sel connector:host_emac1_sel -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\xps_ll_temac_v2_00_a\data\x
ps_ll_temac_v2_1_0.mpd line 267 - floating connection!
warning:edk:2099 - port:bscan_tdi connector:bscan_tdi -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\mdm_v1_00_e\data\mdm_v2_1_0
.mpd line 223 - floating connection!
warning:edk:2099 - port:bscan_reset connector:bscan_reset -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\mdm_v1_00_e\data\mdm_v2_1_0
.mpd line 224 - floating connection!
warning:edk:2099 - port:bscan_shift connector:bscan_shift -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\mdm_v1_00_e\data\mdm_v2_1_0
.mpd line 225 - floating connection!
warning:edk:2099 - port:bscan_update connector:bscan_update -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\mdm_v1_00_e\data\mdm_v2_1_0
.mpd line 226 - floating connection!
warning:edk:2099 - port:bscan_capture connector:bscan_capture -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\mdm_v1_00_e\data\mdm_v2_1_0
.mpd line 227 - floating connection!
warning:edk:2099 - port:bscan_sel1 connector:bscan_sel1 -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\mdm_v1_00_e\data\mdm_v2_1_0
.mpd line 228 - floating connection!
warning:edk:2099 - port:bscan_drck1 connector:bscan_drck1 -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\mdm_v1_00_e\data\mdm_v2_1_0
.mpd line 229 - floating connection!
解决方案：官方给出的解决方案是忽略warning，对结果不影响。
（6）.error: 1 constraint not met.
par could not meet all timing constraints. a bitstream will not be generated.
to disable the par timing check:
1> disable the treat timing closure failure as error option from the project options dialog in xps.
or
2> type following at the xps prompt:
xps% xset enable_par_timing_error 0
解决办法：在xps的project菜单栏选择project options中选择hierarchy and flow将treating
timing closure failure as an error前面的√去掉即可。
（7）.error:place:713 - iob component fpga_0_ddr2_sdram_ddr2_dq and
iodelay
component
ddr2_sdram/ddr2_sdram/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g
en_dq[13].u_iob_dq/u_idelay_dq must be placed adjacent to each other
into
the same i/o tile in order to route net
ddr2_sdram/ddr2_sdram/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g
en_dq[13].u_iob_dq/dq_in. the following issue has been detected:
some of the logic associated with this structure is locked. this should
cause
the rest of the logic to be locked.a problem was found at site
iodelay_x0y56
where we must place iodelay
ddr2_sdram/ddr2_sdram/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge
n_dq[13].u_iob_dq/u_idelay_dq in order to satisfy the relative
placement
requirements of this logic. iodelay
ddr2_sdram/ddr2_sdram/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge
n_dqs[0].u_iob_dqs/u_iodelay_dq_ce appears to already be placed there
which
makes this design unplaceable.
解决办法：打开你的工程，在system assembly view的界面下，切换到ports栏下，将fpga_0_ddr2_sdram的下拉框中，找到相应的的项，选中相应的项就可以。
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（1）xupv5_bsb_std_ip时出现了问题，其错误描述如下：
[xupv5_bsb_system.ucf(1110)]: net xps_iic_0_gpo_pin not found. please
verify that:
1. the specified design element actually exists in the original design.
2. the specified object is spelled correctly in the constraint source file.
iostandard=lvcmos33;> [xupv5_bsb_system.ucf(1111)]: net xps_iic_0_gpo_pin
not found. please verify that:
1. the specified design element actually exists in the original design.
2. the specified object is spelled correctly in the constraint source file.
make: *** [__xps/xupv5_bsb_system_routed] error 1
解决办法：打开xupv5_bsb_std_ip文件夹里面的xupv5_bsb_system.mhs文件，
在其80行的位置，将port xps_iic_0_gpo_pin = xps_iic_0_gpo, dir = o, vec = [31:31]注释掉（即在前面加上#即可）或删除。
在其551行的位置，将 port gpo = xps_iic_0_gpo注释掉（即在前面加上#即可）或删除。
保存该文件。
然后打开xupv5_bsb_std_ip文件夹里面的xupv5_bsb_system.ucf文件
在其1110行和1111行的位置，将net xps_iic_0_gpo_pin loc=ak6; # dvi_reset_b
net xps_iic_0_gpo_pin iostandard=lvcmos33;两行删除或者注释掉。
保存该文件即可。
（2）.running drcs for oses, drivers and libraries ...
runnning drc for lwip library...
error:mdt - issued from tcl procedure ::sw_lwip_v3_00_a::lwip_drc line 12
lwip () - no ethernet mac cores are addressable from processor ppc440_0.
lwip requires atleast one emac (xps_ethernetlite | xps_ll_temac) core.
error:mdt - error while running drc for processor ppc440_0...
make: *** [ppc440_0/lib/libxil.a] error 2
done!
看到了这个问题，首先要学会自己找，上面明显提示是lwip出错，我们看一下datasheet就会发现： lwip provides an easy way to add tcp/ip-based networking capability to an embedded systemlwip_v3_00_a in edk provides adapters for the xps_ethernetlite and xps_ll_temac
xilinx? ethernet mac cores, and is based on the lwip stack version 1.2.0. this document
describes how to use lwip_v3_00_a to add networking capability to embedded software. 我们知道了它的作用，那就找吧，反正，xilinx里面是以mhs和mss文件为主线，那就行动吧
解决办法：在mss文件里找到# begin library
parameter library_name = lwip
parameter library_ver = 3.00.a
parameter proc_instance = microblaze_0
parameter api_mode = socket_api
end
将其注释掉或者删除。
（3）.error: failed to add write permission for
d:\..\microblaze_0\libsrc\lcd_ip_v1_00_a\
error:failed to copy
d:\..\drivers\lcd_ip_v1_00_a\src\ to
d:\..\microblaze_0\libsrc\lcd_ip_v1_00_a\
copying files for driver cpu_v1_11_b from
d:\xilinx\11.1\edk\sw\xilinxprocessoriplib\drivers\cpu_v1_11_b\src\ to
error: error while running copy files for processor microblaze_0...
make: *** [microblaze_0/lib/libxil.a] error 2
done!
解决办法：到桌面右键单击我的电脑，选择属性，再选择高级这一栏，单击环境变量，在新弹出的环境变量对话框下，单击系统变量的新建按钮，输入变量名：cygwin
在变量值中输入：nontsec，单击ok，重新启动xps，重新编译即可。
（4）.error:edk - d:\xilinx\sample\xupv5_bsb_std_ip\xupv5_bsb_system.mhs line 392 - parameter c_left_pos has value 7 which does not fall in the range (0:c_split-1), specified in mpd
error:edk - d:\xilinx\sample\xupv5_bsb_std_ip\xupv5_bsb_system.mhs line 393 - parameter c_split has value 31 which does not fall in the range (1:c_size_in-1), specified in mpd
error:edk - d:\xilinx\sample\xupv5_bsb_std_ip\xupv5_bsb_system.mhs line 392 - parameter c_left_pos has value 7 which does not fall in the range (0:c_split-1), specified in mpd
error:edk - d:\xilinx\sample\xupv5_bsb_std_ip\xupv5_bsb_system.mhs line 393 - parameter c_split has value 31 which does not fall in the range (1:c_size_in-1), specified in mpd
解决办法：this error can be safely ignored as it is being generated incorrectly. the project will implement.
官方给出的答复是忽略这个错误。
（5）.warning:edk:2099 - port:i_addrtag connector:ilmb_m_addrtag -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\microblaze_v7_20_a\data\mic
roblaze_v2_1_0.mpd line 232 - floating connection!
warning:edk:2099 - port:d_addrtag connector:dlmb_m_addrtag -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\microblaze_v7_20_a\data\mic
roblaze_v2_1_0.mpd line 273 - floating connection!
warning:edk:2099 - port:hostmiimsel connector:host_mii_sel -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\xps_ll_temac_v2_00_a\data\x
ps_ll_temac_v2_1_0.mpd line 264 - floating connection!
warning:edk:2099 - port:hostreq connector:host_req -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\xps_ll_temac_v2_00_a\data\x
ps_ll_temac_v2_1_0.mpd line 265 - floating connection!
warning:edk:2099 - port:hostaddr connector:host_addr -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\xps_ll_temac_v2_00_a\data\x
ps_ll_temac_v2_1_0.mpd line 266 - floating connection!
warning:edk:2099 - port:hostemac1sel connector:host_emac1_sel -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\xps_ll_temac_v2_00_a\data\x
ps_ll_temac_v2_1_0.mpd line 267 - floating connection!
warning:edk:2099 - port:bscan_tdi connector:bscan_tdi -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\mdm_v1_00_e\data\mdm_v2_1_0
.mpd line 223 - floating connection!
warning:edk:2099 - port:bscan_reset connector:bscan_reset -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\mdm_v1_00_e\data\mdm_v2_1_0
.mpd line 224 - floating connection!
warning:edk:2099 - port:bscan_shift connector:bscan_shift -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\mdm_v1_00_e\data\mdm_v2_1_0
.mpd line 225 - floating connection!
warning:edk:2099 - port:bscan_update connector:bscan_update -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\mdm_v1_00_e\data\mdm_v2_1_0
.mpd line 226 - floating connection!
warning:edk:2099 - port:bscan_capture connector:bscan_capture -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\mdm_v1_00_e\data\mdm_v2_1_0
.mpd line 227 - floating connection!
warning:edk:2099 - port:bscan_sel1 connector:bscan_sel1 -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\mdm_v1_00_e\data\mdm_v2_1_0
.mpd line 228 - floating connection!
warning:edk:2099 - port:bscan_drck1 connector:bscan_drck1 -
d:\xilinx\11.1\edk\hw\xilinxprocessoriplib\pcores\mdm_v1_00_e\data\mdm_v2_1_0
.mpd line 229 - floating connection!
解决方案：官方给出的解决方案是忽略warning，对结果不影响。
（6）.error: 1 constraint not met.
par could not meet all timing constraints. a bitstream will not be generated.
to disable the par timing check:
1> disable the treat timing closure failure as error option from the project options dialog in xps.
or
2> type following at the xps prompt:
xps% xset enable_par_timing_error 0
解决办法：在xps的project菜单栏选择project options中选择hierarchy and flow将treating
timing closure failure as an error前面的√去掉即可。
（7）.error:place:713 - iob component fpga_0_ddr2_sdram_ddr2_dq and
iodelay
component
ddr2_sdram/ddr2_sdram/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g
en_dq[13].u_iob_dq/u_idelay_dq must be placed adjacent to each other
into
the same i/o tile in order to route net
ddr2_sdram/ddr2_sdram/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g
en_dq[13].u_iob_dq/dq_in. the following issue has been detected:
some of the logic associated with this structure is locked. this should
cause
the rest of the logic to be locked.a problem was found at site
iodelay_x0y56
where we must place iodelay
ddr2_sdram/ddr2_sdram/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge
n_dq[13].u_iob_dq/u_idelay_dq in order to satisfy the relative
placement
requirements of this logic. iodelay
ddr2_sdram/ddr2_sdram/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge
n_dqs[0].u_iob_dqs/u_iodelay_dq_ce appears to already be placed there
which
makes this design unplaceable.
解决办法：打开你的工程，在system assembly view的界面下，切换到ports栏下，将fpga_0_ddr2_sdram的下拉框中，找到相应的的项，选中相应的项就可以。
三星电子任命权五铉为新CEO 崔志成遭架空
京东方将在2021年下半年推出化Micro OLED显示屏
Vishay采用小尺寸封装的365nm波长的中功率UV LED具有超长使用寿命
pcie和pci插槽有什么区别
南腊新区助力勐腊县构建以5G为引领的新一代信息基础设施体系
LX110T的板子上跑demo的时候遇到的一些错误的解决办法总结
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