FPGA设计与应用之基于AD9833芯片的信号发生器设计
改了好几天的程序，不知道说什么，直接上代码吧
/****************************************************/
/****************************************************/
/* made by jerry */
/****************************************************/
/****************************************************/
`timescale 1ns/1ns
module happy(
clk,
rst_n,
sclk,
din,
fsy
);
//黄正
input clk; //系统输入时钟
input rst_n; //复位信号
output reg din; //ad9833输入数据
output reg fsy; //数据输入控制信号
output reg sclk; //串行通信时钟
/*
串行通信：采用三线spi（serial串行 peripheral外设 interface接口）形式
几个重要的串行接口说明
sclk:串行时钟输入，数据在时钟下降沿输入ad9833
din:串行数据输入接口，输入数据位数为16bit
fsync：低有效控制输入active low control input. this is the frame synchronization signal for the input data. when fsync is taken low, the internal logic is informed that a new word is
being loaded into the device.输入的帧同步信号数据，当fsync变低时，会通知内部逻辑一个字节输入完毕。数据只有在fsync为低电平时才可以向芯片输入
在第16个sclk下降沿之后fsync拉高，
*/
wire trans_done; //2 byte 数据传输完成标志信号
reg[3:0]cishu; //字通信次数寄存器，用于控制传输进程
reg[3:0]div_cnt; //分频计数器，用于序列机控制
reg sclk2x; //2倍sclk的采样时钟
reg [8:0]sclk_gen_cnt;//sclk生成暨序列机计数器
reg en;//转换使能信号
parameter div_param=2;
parameter
dac_data0=16'h2100, //0010_0001_0000_0000 db13=1表示即将两次写入完整频率控制字，同时将寄存器复位
dac_data1=16'h69f1, //6886 //0110_1001_1111_0001: 低14bit是输入的频率数据，db15:db14=01表示选择频率寄存器feg0
dac_data2=16'h4000, // 0100_0000_0000_0000 高14bit=0
dac_data3=16'hc000, //1100_0000_0000_0000:选择相位寄存器0，data=0
dac_data4=16'h0100, // 0000_0001_0000_0000
dac_data5=16'h2100, //选择数据一次写入，db13&rest=1
dac_data6=16'h2000, //设置相位寄存器0作为相位累加器
dac_data7=16'h2000; //选择正弦波
//数据传输使能控制模块
always@(posedge clk or negedge rst_n)
if(!rst_n)
en <=#1 1'b1;
else if(trans_done)
en <=#1 1'b0;
else
en <=en;
//完整数据传输完成标志信号
assign trans_done = (cishu ==4'd8 ) && sclk2x;
//生成2倍sclk使时钟计数器
always@(posedge clk or negedge rst_n)
if(!rst_n)
div_cnt <= #1 4'd0;
else if(en)begin
if(div_cnt == (div_param - 1'b1))
div_cnt <= #1 4'd0;
else
div_cnt <= #1 div_cnt + 1'b1;
end else
div_cnt <= #1 4'd0;
//生成2倍sclk时钟计数器 结果是使sclk周期为40ns完美
always@(posedge clk or negedge rst_n)
if(!rst_n)
sclk2x <= #1 1'b0;
else if(en && (div_cnt == (div_param - 1'b1)))
sclk2x <= #1 1'b1;
else
sclk2x <= #1 1'b0;
//生成序列计数器
always@(posedge clk or negedge rst_n)
if(!rst_n)
sclk_gen_cnt <= #1 9'd0;
else if(sclk2x && en)
begin
if(sclk_gen_cnt == 9'd271)
sclk_gen_cnt <= #1 9'd271;
else
sclk_gen_cnt <= #1 sclk_gen_cnt + 1'b1;
end
else
sclk_gen_cnt <= #1 sclk_gen_cnt;
/*
*******************依次将数据移出到芯片********************
*/
always@(posedge clk or negedge rst_n)
if(!rst_n)
begin
din <=#0 1'b1;
sclk <=#1 1'b1;
fsy <=1'b1;
cishu<=4'd0;
end
else if((!trans_done)&&sclk2x)
begin
case(sclk_gen_cnt)
/******************************************************/
/*传输 dac_data0*/
/******************************************************/
0:
begin
din <= #1 dac_data0[15];
fsy<=1'b0;
sclk <= #5 1'b0;
end
1,3,5,7,9,11,13,15,17,19,21,23,25,27,29:
begin
sclk <= #1 1'b1;
end
31:
begin
sclk <= #1 1'b1;
fsy<= 1'b1;
end
2: begin din <= #1 dac_data0[14]; sclk <= #1 1'b0; end
4: begin din <= #1 dac_data0[13]; sclk <= #1 1'b0; end
6: begin din <= #1 dac_data0[12]; sclk <= #1 1'b0; end
8: begin din <= #1 dac_data0[11]; sclk <= #1 1'b0; end
10: begin din <= #1 dac_data0[10]; sclk <= #1 1'b0; end
12: begin din <= #1 dac_data0[9]; sclk <= #1 1'b0; end
14: begin din <= #1 dac_data0[8]; sclk <= #1 1'b0; end
16: begin din <= #1 dac_data0[7]; sclk <= #1 1'b0; end
18: begin din <= #1 dac_data0[6]; sclk <= #1 1'b0; end
20: begin din <= #1 dac_data0[5]; sclk <= #1 1'b0; end
22: begin din <= #1 dac_data0[4]; sclk <= #1 1'b0; end
24: begin din <= #1 dac_data0[3]; sclk <= #1 1'b0; end
26: begin din <= #1 dac_data0[2]; sclk <= #1 1'b0; end
28: begin din <= #1 dac_data0[1]; sclk <= #1 1'b0; end
30: begin din <= #1 dac_data0[0]; sclk <= #1 1'b0; end
32:
begin
sclk <= #1 1'b0;
end
33:
begin
sclk<=1'b1;
cishu<=4'd1;
end
/********************************************************/
/*传输 dac_data1*/
/********************************************************/
34:
begin
din <= #1 dac_data1[15];
fsy<=1'b0;
sclk <= #5 1'b0;
end
35,37,39,41,43,45,47,49,51,53,55,57,59,61,63:
begin
sclk <= #1 1'b1;
end
65:
begin
sclk <= #1 1'b1;
fsy<=#1 1'b1;
end
36: begin din <= #1 dac_data1[14]; sclk <= #1 1'b0; end
38: begin din <= #1 dac_data1[13]; sclk <= #1 1'b0; end
40: begin din <= #1 dac_data1[12]; sclk <= #1 1'b0; end
42: begin din <= #1 dac_data1[11]; sclk <= #1 1'b0; end
44: begin din <= #1 dac_data1[10]; sclk <= #1 1'b0; end
46: begin din <= #1 dac_data1[9]; sclk <= #1 1'b0; end
48: begin din <= #1 dac_data1[8]; sclk <= #1 1'b0; end
50: begin din <= #1 dac_data1[7]; sclk <= #1 1'b0; end
52: begin din <= #1 dac_data1[6]; sclk <= #1 1'b0; end
54: begin din <= #1 dac_data1[5]; sclk <= #1 1'b0; end
56: begin din <= #1 dac_data1[4]; sclk <= #1 1'b0; end
58: begin din <= #1 dac_data1[3]; sclk <= #1 1'b0; end
60: begin din <= #1 dac_data1[2]; sclk <= #1 1'b0; end
62: begin din <= #1 dac_data1[1]; sclk <= #1 1'b0; end
64: begin din <= #1 dac_data1[0]; sclk <= #1 1'b0; end
66:
begin
sclk <= #1 1'b0;
// fsy<=#1 1'b1;
end
67:
begin
sclk<=1'b1;
cishu<=4'd2;
end
/***********************************************************/
/*传输 dac_data2*/
/*******************************************************/
68:
begin
din <= #1 dac_data2[15];
fsy<=1'b0;
sclk <= #5 1'b0;
end
69,71,73,75,77,79,81,83,85,87,89,91,93,95,97:
begin
sclk <= #1 1'b1;
end
99:
begin
sclk <= #1 1'b1;
fsy<=#1 1'b1;
end
70: begin din <= #1 dac_data2[14]; sclk <= #1 1'b0; end
72: begin din <= #1 dac_data2[13]; sclk <= #1 1'b0; end
74: begin din <= #1 dac_data2[12]; sclk <= #1 1'b0; end
76: begin din <= #1 dac_data2[11]; sclk <= #1 1'b0; end
78: begin din <= #1 dac_data2[10]; sclk <= #1 1'b0; end
80: begin din <= #1 dac_data2[9]; sclk <= #1 1'b0; end
82: begin din <= #1 dac_data2[8]; sclk <= #1 1'b0; end
84: begin din <= #1 dac_data2[7]; sclk <= #1 1'b0; end
86: begin din <= #1 dac_data2[6]; sclk <= #1 1'b0; end
88: begin din <= #1 dac_data2[5]; sclk <= #1 1'b0; end
90: begin din <= #1 dac_data2[4]; sclk <= #1 1'b0; end
92: begin din <= #1 dac_data2[3]; sclk <= #1 1'b0; end
94: begin din <= #1 dac_data2[2]; sclk <= #1 1'b0; end
96: begin din <= #1 dac_data2[1]; sclk <= #1 1'b0; end
98: begin din <= #1 dac_data2[0]; sclk <= #1 1'b0; end
100:
begin
sclk <= #1 1'b0;
// fsy<=#1 1'b1;
end
101:
begin
sclk<=1'b1;
// fsy<=#2 1'b1;
cishu<=4'd3;
end
/************************************************************************/
/*传输 dac_data3 */
/************************************************************************/
102:
begin
din <= #1 dac_data3[15];
fsy<=1'b0;
sclk <= #5 1'b0;
end
103,105,107,109,111,113,115,117,119,121,123,125,127,129,131:
begin
sclk <= #1 1'b1;
end
133:
begin
sclk <= #1 1'b1;
fsy<=#1 1'b1;
end
104: begin din <= #1 dac_data3[14]; sclk <= #1 1'b0; end
106: begin din <= #1 dac_data3[13]; sclk <= #1 1'b0; end
108: begin din <= #1 dac_data3[12]; sclk <= #1 1'b0; end
110: begin din <= #1 dac_data3[11]; sclk <= #1 1'b0; end
112: begin din <= #1 dac_data3[10]; sclk <= #1 1'b0; end
114: begin din <= #1 dac_data3[9]; sclk <= #1 1'b0; end
116: begin din <= #1 dac_data3[8]; sclk <= #1 1'b0; end
118: begin din <= #1 dac_data3[7]; sclk <= #1 1'b0; end
120: begin din <= #1 dac_data3[6]; sclk <= #1 1'b0; end
122: begin din <= #1 dac_data3[5]; sclk <= #1 1'b0; end
124: begin din <= #1 dac_data3[4]; sclk <= #1 1'b0; end
126: begin din <= #1 dac_data3[3]; sclk <= #1 1'b0; end
128: begin din <= #1 dac_data3[2]; sclk <= #1 1'b0; end
130: begin din <= #1 dac_data3[1]; sclk <= #1 1'b0; end
132: begin din <= #1 dac_data3[0]; sclk <= #1 1'b0; end
134:
begin
sclk <= #1 1'b0;
// fsy<=#1 1'b1;
end
135:
begin
sclk<=1'b1;
cishu<=4'd4;
end
/************************************************************************/
/*传输 dac_data4*/
/************************************************************************/
136:
begin
din <= #1 dac_data4[15];
fsy<=1'b0;
sclk <= #5 1'b0;
end
137,139,141,143,145,147,149,151,153,155,157,159,161,163,165:
begin
sclk <= #1 1'b1;
end
167:
begin
sclk <= #1 1'b1;
fsy<=#1 1'b1;
end
138: begin din <= #1 dac_data4[14]; sclk <= #1 1'b0; end
140: begin din <= #1 dac_data4[13]; sclk <= #1 1'b0; end
142: begin din <= #1 dac_data4[12]; sclk <= #1 1'b0; end
144: begin din <= #1 dac_data4[11]; sclk <= #1 1'b0; end
146: begin din <= #1 dac_data4[10]; sclk <= #1 1'b0; end
148: begin din <= #1 dac_data4[9]; sclk <= #1 1'b0; end
150: begin din <= #1 dac_data4[8]; sclk <= #1 1'b0; end
152: begin din <= #1 dac_data4[7]; sclk <= #1 1'b0; end
154: begin din <= #1 dac_data4[6]; sclk <= #1 1'b0; end
156: begin din <= #1 dac_data4[5]; sclk <= #1 1'b0; end
158: begin din <= #1 dac_data4[4]; sclk <= #1 1'b0; end
160: begin din <= #1 dac_data4[3]; sclk <= #1 1'b0; end
162: begin din <= #1 dac_data4[2]; sclk <= #1 1'b0; end
164: begin din <= #1 dac_data4[1]; sclk <= #1 1'b0; end
166: begin din <= #1 dac_data4[0]; sclk <= #1 1'b0; end
168:
begin
sclk <= #1 1'b0;
end
169:
begin
sclk<=1'b1;
// fsy<=#2 1'b1;
cishu<=4'd5;
end
/************************************************************************/
/*传输 dac_data5*/
/************************************************************************/
170:
begin
din <= #1 dac_data5[15];
fsy<=1'b0;
sclk <= #5 1'b0;
end
171,173,175,177,179,181,183,185,187,189,191,193,195,197,199:
begin
sclk <= #1 1'b1;
end
201:
begin
sclk <= #1 1'b1;
fsy<=#1 1'b1;
end
172: begin din <= #1 dac_data5[14]; sclk <= #1 1'b0; end
174: begin din <= #1 dac_data5[13]; sclk <= #1 1'b0; end
176: begin din <= #1 dac_data5[12]; sclk <= #1 1'b0; end
178: begin din <= #1 dac_data5[11]; sclk <= #1 1'b0; end
180: begin din <= #1 dac_data5[10]; sclk <= #1 1'b0; end
182: begin din <= #1 dac_data5[9]; sclk <= #1 1'b0; end
184: begin din <= #1 dac_data5[8]; sclk <= #1 1'b0; end
186: begin din <= #1 dac_data5[7]; sclk <= #1 1'b0; end
188: begin din <= #1 dac_data5[6]; sclk <= #1 1'b0; end
190: begin din <= #1 dac_data5[5]; sclk <= #1 1'b0; end
192: begin din <= #1 dac_data5[4]; sclk <= #1 1'b0; end
194: begin din <= #1 dac_data5[3]; sclk <= #1 1'b0; end
196: begin din <= #1 dac_data5[2]; sclk <= #1 1'b0; end
198: begin din <= #1 dac_data5[1]; sclk <= #1 1'b0; end
200: begin din <= #1 dac_data5[0]; sclk <= #1 1'b0; end
202:
begin
sclk <= #1 1'b0;
end
203:
begin
sclk<=1'b1;
// fsy<=#2 1'b1;
cishu<=4'd6;
end
/************************************************************************/
/*传输 dac_data6*/
/************************************************************************/
204:
begin
din <= #1 dac_data6[15];
fsy<=1'b0;
sclk <= #5 1'b0;
end
205,207,209,211,213,215,217,219,221,223,225,227,229,231,233:
begin
sclk <= #1 1'b1;
end
235:
begin
sclk <= #1 1'b1;
fsy<=#1 1'b1;
end
206: begin din <= #1 dac_data6[14]; sclk <= #1 1'b0; end
208: begin din <= #1 dac_data6[13]; sclk <= #1 1'b0; end
210: begin din <= #1 dac_data6[12]; sclk <= #1 1'b0; end
212: begin din <= #1 dac_data6[11]; sclk <= #1 1'b0; end
214: begin din <= #1 dac_data6[10]; sclk <= #1 1'b0; end
216: begin din <= #1 dac_data6[9]; sclk <= #1 1'b0; end
218: begin din <= #1 dac_data6[8]; sclk <= #1 1'b0; end
220: begin din <= #1 dac_data6[7]; sclk <= #1 1'b0; end
222: begin din <= #1 dac_data6[6]; sclk <= #1 1'b0; end
224: begin din <= #1 dac_data6[5]; sclk <= #1 1'b0; end
226: begin din <= #1 dac_data6[4]; sclk <= #1 1'b0; end
228: begin din <= #1 dac_data6[3]; sclk <= #1 1'b0; end
230: begin din <= #1 dac_data6[2]; sclk <= #1 1'b0; end
232: begin din <= #1 dac_data6[1]; sclk <= #1 1'b0; end
234: begin din <= #1 dac_data6[0]; sclk <= #1 1'b0; end
236:
begin
sclk <= #1 1'b0;
// fsy<=#1 1'b1;
end
237:
begin
sclk<=1'b1;
cishu<=4'd7;
end
/************************************************************************/
/*传输 dac_data7*/
/************************************************************************/
238:
begin
din <= #1 dac_data7[15];
sclk <= #5 1'b0;
fsy<=1'b0;
end
239,241,243,245,247,249,251,253,255,257,259,261,263,265,267:
begin
sclk <= #1 1'b1;
end
269:
begin
sclk <= #1 1'b1;
fsy<=#1 1'b1;
end
240: begin din <= #1 dac_data7[14]; sclk <= #1 1'b0; end
242: begin din <= #1 dac_data7[13]; sclk <= #1 1'b0; end
244: begin din <= #1 dac_data7[12]; sclk <= #1 1'b0; end
246: begin din <= #1 dac_data7[11]; sclk <= #1 1'b0; end
248: begin din <= #1 dac_data7[10]; sclk <= #1 1'b0; end
250: begin din <= #1 dac_data7[9]; sclk <= #1 1'b0; end
252: begin din <= #1 dac_data7[8]; sclk <= #1 1'b0; end
254: begin din <= #1 dac_data7[7]; sclk <= #1 1'b0; end
256: begin din <= #1 dac_data7[6]; sclk <= #1 1'b0; end
258: begin din <= #1 dac_data7[5]; sclk <= #1 1'b0; end
260: begin din <= #1 dac_data7[4]; sclk <= #1 1'b0; end
262: begin din <= #1 dac_data7[3]; sclk <= #1 1'b0; end
264: begin din <= #1 dac_data7[2]; sclk <= #1 1'b0; end
266: begin din <= #1 dac_data7[1]; sclk <= #1 1'b0; end
268: begin din <= #1 dac_data7[0]; sclk <= #1 1'b0; end
270:
begin
sclk <= #1 1'b0;
// fsy<=#1 1'b1;
end
271:
begin
sclk<=1'b1;
cishu<=4'd8;
end
default:;
endcase
end
endmodule
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/****************************************************/
/****************************************************/
/* made by jerry */
/****************************************************/
/****************************************************/
`timescale 1ns/1ns
module happy(
clk,
rst_n,
sclk,
din,
fsy
);
//黄正
input clk; //系统输入时钟
input rst_n; //复位信号
output reg din; //ad9833输入数据
output reg fsy; //数据输入控制信号
output reg sclk; //串行通信时钟
/*
串行通信：采用三线spi（serial串行 peripheral外设 interface接口）形式
几个重要的串行接口说明
sclk:串行时钟输入，数据在时钟下降沿输入ad9833
din:串行数据输入接口，输入数据位数为16bit
fsync：低有效控制输入active low control input. this is the frame synchronization signal for the input data. when fsync is taken low, the internal logic is informed that a new word is
being loaded into the device.输入的帧同步信号数据，当fsync变低时，会通知内部逻辑一个字节输入完毕。数据只有在fsync为低电平时才可以向芯片输入
在第16个sclk下降沿之后fsync拉高，
*/
wire trans_done; //2 byte 数据传输完成标志信号
reg[3:0]cishu; //字通信次数寄存器，用于控制传输进程
reg[3:0]div_cnt; //分频计数器，用于序列机控制
reg sclk2x; //2倍sclk的采样时钟
reg [8:0]sclk_gen_cnt;//sclk生成暨序列机计数器
reg en;//转换使能信号
parameter div_param=2;
parameter
dac_data0=16'h2100, //0010_0001_0000_0000 db13=1表示即将两次写入完整频率控制字，同时将寄存器复位
dac_data1=16'h69f1, //6886 //0110_1001_1111_0001: 低14bit是输入的频率数据，db15:db14=01表示选择频率寄存器feg0
dac_data2=16'h4000, // 0100_0000_0000_0000 高14bit=0
dac_data3=16'hc000, //1100_0000_0000_0000:选择相位寄存器0，data=0
dac_data4=16'h0100, // 0000_0001_0000_0000
dac_data5=16'h2100, //选择数据一次写入，db13&rest=1
dac_data6=16'h2000, //设置相位寄存器0作为相位累加器
dac_data7=16'h2000; //选择正弦波
//数据传输使能控制模块
always@(posedge clk or negedge rst_n)
if(!rst_n)
en <=#1 1'b1;
else if(trans_done)
en <=#1 1'b0;
else
en <=en;
//完整数据传输完成标志信号
assign trans_done = (cishu ==4'd8 ) && sclk2x;
//生成2倍sclk使时钟计数器
always@(posedge clk or negedge rst_n)
if(!rst_n)
div_cnt <= #1 4'd0;
else if(en)begin
if(div_cnt == (div_param - 1'b1))
div_cnt <= #1 4'd0;
else
div_cnt <= #1 div_cnt + 1'b1;
end else
div_cnt <= #1 4'd0;
//生成2倍sclk时钟计数器 结果是使sclk周期为40ns完美
always@(posedge clk or negedge rst_n)
if(!rst_n)
sclk2x <= #1 1'b0;
else if(en && (div_cnt == (div_param - 1'b1)))
sclk2x <= #1 1'b1;
else
sclk2x <= #1 1'b0;
//生成序列计数器
always@(posedge clk or negedge rst_n)
if(!rst_n)
sclk_gen_cnt <= #1 9'd0;
else if(sclk2x && en)
begin
if(sclk_gen_cnt == 9'd271)
sclk_gen_cnt <= #1 9'd271;
else
sclk_gen_cnt <= #1 sclk_gen_cnt + 1'b1;
end
else
sclk_gen_cnt <= #1 sclk_gen_cnt;
/*
*******************依次将数据移出到芯片********************
*/
always@(posedge clk or negedge rst_n)
if(!rst_n)
begin
din <=#0 1'b1;
sclk <=#1 1'b1;
fsy <=1'b1;
cishu<=4'd0;
end
else if((!trans_done)&&sclk2x)
begin
case(sclk_gen_cnt)
/******************************************************/
/*传输 dac_data0*/
/******************************************************/
0:
begin
din <= #1 dac_data0[15];
fsy<=1'b0;
sclk <= #5 1'b0;
end
1,3,5,7,9,11,13,15,17,19,21,23,25,27,29:
begin
sclk <= #1 1'b1;
end
31:
begin
sclk <= #1 1'b1;
fsy<= 1'b1;
end
2: begin din <= #1 dac_data0[14]; sclk <= #1 1'b0; end
4: begin din <= #1 dac_data0[13]; sclk <= #1 1'b0; end
6: begin din <= #1 dac_data0[12]; sclk <= #1 1'b0; end
8: begin din <= #1 dac_data0[11]; sclk <= #1 1'b0; end
10: begin din <= #1 dac_data0[10]; sclk <= #1 1'b0; end
12: begin din <= #1 dac_data0[9]; sclk <= #1 1'b0; end
14: begin din <= #1 dac_data0[8]; sclk <= #1 1'b0; end
16: begin din <= #1 dac_data0[7]; sclk <= #1 1'b0; end
18: begin din <= #1 dac_data0[6]; sclk <= #1 1'b0; end
20: begin din <= #1 dac_data0[5]; sclk <= #1 1'b0; end
22: begin din <= #1 dac_data0[4]; sclk <= #1 1'b0; end
24: begin din <= #1 dac_data0[3]; sclk <= #1 1'b0; end
26: begin din <= #1 dac_data0[2]; sclk <= #1 1'b0; end
28: begin din <= #1 dac_data0[1]; sclk <= #1 1'b0; end
30: begin din <= #1 dac_data0[0]; sclk <= #1 1'b0; end
32:
begin
sclk <= #1 1'b0;
end
33:
begin
sclk<=1'b1;
cishu<=4'd1;
end
/********************************************************/
/*传输 dac_data1*/
/********************************************************/
34:
begin
din <= #1 dac_data1[15];
fsy<=1'b0;
sclk <= #5 1'b0;
end
35,37,39,41,43,45,47,49,51,53,55,57,59,61,63:
begin
sclk <= #1 1'b1;
end
65:
begin
sclk <= #1 1'b1;
fsy<=#1 1'b1;
end
36: begin din <= #1 dac_data1[14]; sclk <= #1 1'b0; end
38: begin din <= #1 dac_data1[13]; sclk <= #1 1'b0; end
40: begin din <= #1 dac_data1[12]; sclk <= #1 1'b0; end
42: begin din <= #1 dac_data1[11]; sclk <= #1 1'b0; end
44: begin din <= #1 dac_data1[10]; sclk <= #1 1'b0; end
46: begin din <= #1 dac_data1[9]; sclk <= #1 1'b0; end
48: begin din <= #1 dac_data1[8]; sclk <= #1 1'b0; end
50: begin din <= #1 dac_data1[7]; sclk <= #1 1'b0; end
52: begin din <= #1 dac_data1[6]; sclk <= #1 1'b0; end
54: begin din <= #1 dac_data1[5]; sclk <= #1 1'b0; end
56: begin din <= #1 dac_data1[4]; sclk <= #1 1'b0; end
58: begin din <= #1 dac_data1[3]; sclk <= #1 1'b0; end
60: begin din <= #1 dac_data1[2]; sclk <= #1 1'b0; end
62: begin din <= #1 dac_data1[1]; sclk <= #1 1'b0; end
64: begin din <= #1 dac_data1[0]; sclk <= #1 1'b0; end
66:
begin
sclk <= #1 1'b0;
// fsy<=#1 1'b1;
end
67:
begin
sclk<=1'b1;
cishu<=4'd2;
end
/***********************************************************/
/*传输 dac_data2*/
/*******************************************************/
68:
begin
din <= #1 dac_data2[15];
fsy<=1'b0;
sclk <= #5 1'b0;
end
69,71,73,75,77,79,81,83,85,87,89,91,93,95,97:
begin
sclk <= #1 1'b1;
end
99:
begin
sclk <= #1 1'b1;
fsy<=#1 1'b1;
end
70: begin din <= #1 dac_data2[14]; sclk <= #1 1'b0; end
72: begin din <= #1 dac_data2[13]; sclk <= #1 1'b0; end
74: begin din <= #1 dac_data2[12]; sclk <= #1 1'b0; end
76: begin din <= #1 dac_data2[11]; sclk <= #1 1'b0; end
78: begin din <= #1 dac_data2[10]; sclk <= #1 1'b0; end
80: begin din <= #1 dac_data2[9]; sclk <= #1 1'b0; end
82: begin din <= #1 dac_data2[8]; sclk <= #1 1'b0; end
84: begin din <= #1 dac_data2[7]; sclk <= #1 1'b0; end
86: begin din <= #1 dac_data2[6]; sclk <= #1 1'b0; end
88: begin din <= #1 dac_data2[5]; sclk <= #1 1'b0; end
90: begin din <= #1 dac_data2[4]; sclk <= #1 1'b0; end
92: begin din <= #1 dac_data2[3]; sclk <= #1 1'b0; end
94: begin din <= #1 dac_data2[2]; sclk <= #1 1'b0; end
96: begin din <= #1 dac_data2[1]; sclk <= #1 1'b0; end
98: begin din <= #1 dac_data2[0]; sclk <= #1 1'b0; end
100:
begin
sclk <= #1 1'b0;
// fsy<=#1 1'b1;
end
101:
begin
sclk<=1'b1;
// fsy<=#2 1'b1;
cishu<=4'd3;
end
/************************************************************************/
/*传输 dac_data3 */
/************************************************************************/
102:
begin
din <= #1 dac_data3[15];
fsy<=1'b0;
sclk <= #5 1'b0;
end
103,105,107,109,111,113,115,117,119,121,123,125,127,129,131:
begin
sclk <= #1 1'b1;
end
133:
begin
sclk <= #1 1'b1;
fsy<=#1 1'b1;
end
104: begin din <= #1 dac_data3[14]; sclk <= #1 1'b0; end
106: begin din <= #1 dac_data3[13]; sclk <= #1 1'b0; end
108: begin din <= #1 dac_data3[12]; sclk <= #1 1'b0; end
110: begin din <= #1 dac_data3[11]; sclk <= #1 1'b0; end
112: begin din <= #1 dac_data3[10]; sclk <= #1 1'b0; end
114: begin din <= #1 dac_data3[9]; sclk <= #1 1'b0; end
116: begin din <= #1 dac_data3[8]; sclk <= #1 1'b0; end
118: begin din <= #1 dac_data3[7]; sclk <= #1 1'b0; end
120: begin din <= #1 dac_data3[6]; sclk <= #1 1'b0; end
122: begin din <= #1 dac_data3[5]; sclk <= #1 1'b0; end
124: begin din <= #1 dac_data3[4]; sclk <= #1 1'b0; end
126: begin din <= #1 dac_data3[3]; sclk <= #1 1'b0; end
128: begin din <= #1 dac_data3[2]; sclk <= #1 1'b0; end
130: begin din <= #1 dac_data3[1]; sclk <= #1 1'b0; end
132: begin din <= #1 dac_data3[0]; sclk <= #1 1'b0; end
134:
begin
sclk <= #1 1'b0;
// fsy<=#1 1'b1;
end
135:
begin
sclk<=1'b1;
cishu<=4'd4;
end
/************************************************************************/
/*传输 dac_data4*/
/************************************************************************/
136:
begin
din <= #1 dac_data4[15];
fsy<=1'b0;
sclk <= #5 1'b0;
end
137,139,141,143,145,147,149,151,153,155,157,159,161,163,165:
begin
sclk <= #1 1'b1;
end
167:
begin
sclk <= #1 1'b1;
fsy<=#1 1'b1;
end
138: begin din <= #1 dac_data4[14]; sclk <= #1 1'b0; end
140: begin din <= #1 dac_data4[13]; sclk <= #1 1'b0; end
142: begin din <= #1 dac_data4[12]; sclk <= #1 1'b0; end
144: begin din <= #1 dac_data4[11]; sclk <= #1 1'b0; end
146: begin din <= #1 dac_data4[10]; sclk <= #1 1'b0; end
148: begin din <= #1 dac_data4[9]; sclk <= #1 1'b0; end
150: begin din <= #1 dac_data4[8]; sclk <= #1 1'b0; end
152: begin din <= #1 dac_data4[7]; sclk <= #1 1'b0; end
154: begin din <= #1 dac_data4[6]; sclk <= #1 1'b0; end
156: begin din <= #1 dac_data4[5]; sclk <= #1 1'b0; end
158: begin din <= #1 dac_data4[4]; sclk <= #1 1'b0; end
160: begin din <= #1 dac_data4[3]; sclk <= #1 1'b0; end
162: begin din <= #1 dac_data4[2]; sclk <= #1 1'b0; end
164: begin din <= #1 dac_data4[1]; sclk <= #1 1'b0; end
166: begin din <= #1 dac_data4[0]; sclk <= #1 1'b0; end
168:
begin
sclk <= #1 1'b0;
end
169:
begin
sclk<=1'b1;
// fsy<=#2 1'b1;
cishu<=4'd5;
end
/************************************************************************/
/*传输 dac_data5*/
/************************************************************************/
170:
begin
din <= #1 dac_data5[15];
fsy<=1'b0;
sclk <= #5 1'b0;
end
171,173,175,177,179,181,183,185,187,189,191,193,195,197,199:
begin
sclk <= #1 1'b1;
end
201:
begin
sclk <= #1 1'b1;
fsy<=#1 1'b1;
end
172: begin din <= #1 dac_data5[14]; sclk <= #1 1'b0; end
174: begin din <= #1 dac_data5[13]; sclk <= #1 1'b0; end
176: begin din <= #1 dac_data5[12]; sclk <= #1 1'b0; end
178: begin din <= #1 dac_data5[11]; sclk <= #1 1'b0; end
180: begin din <= #1 dac_data5[10]; sclk <= #1 1'b0; end
182: begin din <= #1 dac_data5[9]; sclk <= #1 1'b0; end
184: begin din <= #1 dac_data5[8]; sclk <= #1 1'b0; end
186: begin din <= #1 dac_data5[7]; sclk <= #1 1'b0; end
188: begin din <= #1 dac_data5[6]; sclk <= #1 1'b0; end
190: begin din <= #1 dac_data5[5]; sclk <= #1 1'b0; end
192: begin din <= #1 dac_data5[4]; sclk <= #1 1'b0; end
194: begin din <= #1 dac_data5[3]; sclk <= #1 1'b0; end
196: begin din <= #1 dac_data5[2]; sclk <= #1 1'b0; end
198: begin din <= #1 dac_data5[1]; sclk <= #1 1'b0; end
200: begin din <= #1 dac_data5[0]; sclk <= #1 1'b0; end
202:
begin
sclk <= #1 1'b0;
end
203:
begin
sclk<=1'b1;
// fsy<=#2 1'b1;
cishu<=4'd6;
end
/************************************************************************/
/*传输 dac_data6*/
/************************************************************************/
204:
begin
din <= #1 dac_data6[15];
fsy<=1'b0;
sclk <= #5 1'b0;
end
205,207,209,211,213,215,217,219,221,223,225,227,229,231,233:
begin
sclk <= #1 1'b1;
end
235:
begin
sclk <= #1 1'b1;
fsy<=#1 1'b1;
end
206: begin din <= #1 dac_data6[14]; sclk <= #1 1'b0; end
208: begin din <= #1 dac_data6[13]; sclk <= #1 1'b0; end
210: begin din <= #1 dac_data6[12]; sclk <= #1 1'b0; end
212: begin din <= #1 dac_data6[11]; sclk <= #1 1'b0; end
214: begin din <= #1 dac_data6[10]; sclk <= #1 1'b0; end
216: begin din <= #1 dac_data6[9]; sclk <= #1 1'b0; end
218: begin din <= #1 dac_data6[8]; sclk <= #1 1'b0; end
220: begin din <= #1 dac_data6[7]; sclk <= #1 1'b0; end
222: begin din <= #1 dac_data6[6]; sclk <= #1 1'b0; end
224: begin din <= #1 dac_data6[5]; sclk <= #1 1'b0; end
226: begin din <= #1 dac_data6[4]; sclk <= #1 1'b0; end
228: begin din <= #1 dac_data6[3]; sclk <= #1 1'b0; end
230: begin din <= #1 dac_data6[2]; sclk <= #1 1'b0; end
232: begin din <= #1 dac_data6[1]; sclk <= #1 1'b0; end
234: begin din <= #1 dac_data6[0]; sclk <= #1 1'b0; end
236:
begin
sclk <= #1 1'b0;
// fsy<=#1 1'b1;
end
237:
begin
sclk<=1'b1;
cishu<=4'd7;
end
/************************************************************************/
/*传输 dac_data7*/
/************************************************************************/
238:
begin
din <= #1 dac_data7[15];
sclk <= #5 1'b0;
fsy<=1'b0;
end
239,241,243,245,247,249,251,253,255,257,259,261,263,265,267:
begin
sclk <= #1 1'b1;
end
269:
begin
sclk <= #1 1'b1;
fsy<=#1 1'b1;
end
240: begin din <= #1 dac_data7[14]; sclk <= #1 1'b0; end
242: begin din <= #1 dac_data7[13]; sclk <= #1 1'b0; end
244: begin din <= #1 dac_data7[12]; sclk <= #1 1'b0; end
246: begin din <= #1 dac_data7[11]; sclk <= #1 1'b0; end
248: begin din <= #1 dac_data7[10]; sclk <= #1 1'b0; end
250: begin din <= #1 dac_data7[9]; sclk <= #1 1'b0; end
252: begin din <= #1 dac_data7[8]; sclk <= #1 1'b0; end
254: begin din <= #1 dac_data7[7]; sclk <= #1 1'b0; end
256: begin din <= #1 dac_data7[6]; sclk <= #1 1'b0; end
258: begin din <= #1 dac_data7[5]; sclk <= #1 1'b0; end
260: begin din <= #1 dac_data7[4]; sclk <= #1 1'b0; end
262: begin din <= #1 dac_data7[3]; sclk <= #1 1'b0; end
264: begin din <= #1 dac_data7[2]; sclk <= #1 1'b0; end
266: begin din <= #1 dac_data7[1]; sclk <= #1 1'b0; end
268: begin din <= #1 dac_data7[0]; sclk <= #1 1'b0; end
270:
begin
sclk <= #1 1'b0;
// fsy<=#1 1'b1;
end
271:
begin
sclk<=1'b1;
cishu<=4'd8;
end
default:;
endcase
end
endmodule
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