芯片控制可编程滤波器-µP-Supervisor
abstract: an application showing how the use of a microprocessor supervisor can be used to program a dual section filter. using the time delay from the reset circuit and strapping it to the power-fail comparator with a delay circuit, the filter can easily be programmed to provide the correct cutoff frequencies during power up using this reset circuit.
certain dual-section filter ics have a common 7-bit port for programming the two cutoff frequencies (fc). if both sections require the same fc, you can strap an appropriate code to the port pins, but other applications require a different fc for each section. in such cases, a microprocessor is the obvious tool for sequentially programming the two filter sections, but lacking a µp, you can do the job without the circuit of figure 1.
figure 1. a µp-supervisory chip (ic1) directs the sequential loading of fc data into the dual, programmable lowpass filter ic2. the circuit reloads this fc data following each power-up.
ic2 is a continuous, dual-lowpass filter containing identical 2nd-order sections a and b. to program desired fc values, obtain corresponding codes from the data sheet and connect each pin of a0-a6 and b0-b6 to 5v (1) or gnd (0) accordingly. (the latches internal to inputs d0-d6 remain transparent because inputs active-low wr and active-low cs are wired low.)
latch ic3 also remains transparent because pin 11 is wired high. the latch outputs (1q-7q) are three-stated when the output control (active-low oc, pin 1) is driven high. when active-low oc is high, therefore, a0-a6 data drives the filter port (d0-d6). when active-low oc is low, b0-b6 data appears at the latch outputs and overrides a0-a6.
the µp-supervisory chip ic1, though normally used to monitor supply voltage and software execution in a µp system, generates directly usable signals for controlling ic2 and ic3: active-low reset (pin 7), which remains low for 50msec after power-up, directs the input port of ic2 first to filter section a, then to section b. active-low pfo (power fail output, pin 5), which goes high in a few milliseconds after active-low reset, provides a properly timed control signal for three-stating the latch outputs of ic3 (figure 2).
figure 2. timing relationships for the figure 1 circuit.
the circuit as shown requires ±5v supplies. to operate on ±2.5v or on 5v alone, connect ic1's gnd pin to the lower supply rail and drive ic2's pin 12 through a resistive divider (see max270 data sheet, figure 3).
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certain dual-section filter ics have a common 7-bit port for programming the two cutoff frequencies (fc). if both sections require the same fc, you can strap an appropriate code to the port pins, but other applications require a different fc for each section. in such cases, a microprocessor is the obvious tool for sequentially programming the two filter sections, but lacking a µp, you can do the job without the circuit of figure 1.
figure 1. a µp-supervisory chip (ic1) directs the sequential loading of fc data into the dual, programmable lowpass filter ic2. the circuit reloads this fc data following each power-up.
ic2 is a continuous, dual-lowpass filter containing identical 2nd-order sections a and b. to program desired fc values, obtain corresponding codes from the data sheet and connect each pin of a0-a6 and b0-b6 to 5v (1) or gnd (0) accordingly. (the latches internal to inputs d0-d6 remain transparent because inputs active-low wr and active-low cs are wired low.)
latch ic3 also remains transparent because pin 11 is wired high. the latch outputs (1q-7q) are three-stated when the output control (active-low oc, pin 1) is driven high. when active-low oc is high, therefore, a0-a6 data drives the filter port (d0-d6). when active-low oc is low, b0-b6 data appears at the latch outputs and overrides a0-a6.
the µp-supervisory chip ic1, though normally used to monitor supply voltage and software execution in a µp system, generates directly usable signals for controlling ic2 and ic3: active-low reset (pin 7), which remains low for 50msec after power-up, directs the input port of ic2 first to filter section a, then to section b. active-low pfo (power fail output, pin 5), which goes high in a few milliseconds after active-low reset, provides a properly timed control signal for three-stating the latch outputs of ic3 (figure 2).
figure 2. timing relationships for the figure 1 circuit.
the circuit as shown requires ±5v supplies. to operate on ±2.5v or on 5v alone, connect ic1's gnd pin to the lower supply rail and drive ic2's pin 12 through a resistive divider (see max270 data sheet, figure 3).
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Oppo Watch智能手表即将发布，或对苹果造成一些压力
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