DS1077/DS1085 EconOscillators的
abstract: proper decoupling is required for the ds1077 and ds1085 econoscillators to optimize the frequency stability of the devices. the article discusses power-supply decoupling, ac output load characteristics, and divider configurations, all of which affect frequency accuracy. if these characteristics are known and taken into consideration, these devices can be configured for optimum frequency stability. the article provides an overview of the required decoupling of the devices.
introductionlaboratory testing has determined the configurations of the ds1077 and ds1085 econoscillators that optimize the frequency stability of devices. in summary, power-supply decoupling, ac output load characteristics, and divider configurations all affect frequency accuracy. if these characteristics are known and taken into consideration, these devices can be configured for optimum frequency stability.
in less extreme cases where these factors are not taken consideration, frequency shifts of 0.5% or more could be encountered. in extreme cases, the combination of excessive supply inductance and output load can react with internal oscillator circuits, in some cases causing the devices to exhibit bistable operating frequencies. the following considerations eliminate the possibilities of these occurrences. these design considerations are not limited to econoscillators, but any device that uses the same type of architecture. these devices include the ds1100(l) 5-tap delay lines, the ds1135(l) 3-in-1 delay lines, and the ds1110, 10-in-1 delay lines.
design considerations are as follows: place 0.1µf and 0.01µf surface-mount, ceramic caps across vcc/gnd as close to the package as possible to reduce the detrimental effects of power-supply inductance. minimize loading of used output ports; board layout should maintain a minimum trace length between the oscillator and the circuitry it is driving. capacitive loading should be minimized. bypass any unused prescalers or dividers internal to the devices. if only one output is used, disable the second output, even if it is not connected into the circuit. select the lowest master oscillator frequency for the application that will generate the desired frequency. if multiple prescaler/divider combinations can be used to generate the same frequency, use the combination that maximizes the prescaler value. high-output loads can be countered with a small inline resistance using the maximum value resistance value, which does not effect output bandwidth. data sheet links, application notes, and online frequency calculators to aid in determining the optimal configurations are available online at www.maxim-ic.com.
ds1077: 5v econoscillator with 2-wire interface:
http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3359
ds1077l: 3.3v econoscillator with 2-wire interface:
http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3143
ds1085: 5v econoscillator frequency synthesizer:
http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3491
ds1085l: 3.3v econoscillator frequency synthesizer:
http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3495
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introductionlaboratory testing has determined the configurations of the ds1077 and ds1085 econoscillators that optimize the frequency stability of devices. in summary, power-supply decoupling, ac output load characteristics, and divider configurations all affect frequency accuracy. if these characteristics are known and taken into consideration, these devices can be configured for optimum frequency stability.
in less extreme cases where these factors are not taken consideration, frequency shifts of 0.5% or more could be encountered. in extreme cases, the combination of excessive supply inductance and output load can react with internal oscillator circuits, in some cases causing the devices to exhibit bistable operating frequencies. the following considerations eliminate the possibilities of these occurrences. these design considerations are not limited to econoscillators, but any device that uses the same type of architecture. these devices include the ds1100(l) 5-tap delay lines, the ds1135(l) 3-in-1 delay lines, and the ds1110, 10-in-1 delay lines.
design considerations are as follows: place 0.1µf and 0.01µf surface-mount, ceramic caps across vcc/gnd as close to the package as possible to reduce the detrimental effects of power-supply inductance. minimize loading of used output ports; board layout should maintain a minimum trace length between the oscillator and the circuitry it is driving. capacitive loading should be minimized. bypass any unused prescalers or dividers internal to the devices. if only one output is used, disable the second output, even if it is not connected into the circuit. select the lowest master oscillator frequency for the application that will generate the desired frequency. if multiple prescaler/divider combinations can be used to generate the same frequency, use the combination that maximizes the prescaler value. high-output loads can be countered with a small inline resistance using the maximum value resistance value, which does not effect output bandwidth. data sheet links, application notes, and online frequency calculators to aid in determining the optimal configurations are available online at www.maxim-ic.com.
ds1077: 5v econoscillator with 2-wire interface:
http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3359
ds1077l: 3.3v econoscillator with 2-wire interface:
http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3143
ds1085: 5v econoscillator frequency synthesizer:
http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3491
ds1085l: 3.3v econoscillator frequency synthesizer:
http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3495
ATA-2021B高压放大器经典应用合集（内附技术指标）
国民技术N32G/N32L通用安全MCU芯片荣获“2020年网络安全创新产品优秀奖”！
索尼KV-W32MHll型子画面无屏显功能
华为新款手机为何引起轰动
GameAbove向东密歇根大学工程与技术学院捐资160万美元，助其提升网络安全项目
DS1077/DS1085 EconOscillators的
一文知道AR的关键能力
四人抢答器电路设计方案汇总（六款模拟电路设计原理图详解）
工程院院士倪光南：世界交易型数据库tpmC指标中，国产数据库已居第三
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SES展示全球首个容量超过100 Ah的锂金属电池
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SMFT-1000多功能光伏I-V曲线测试仪
爱立信携手TIM探索增强型LTE现网部署vRAN新方式
Silicon Labs参考设计帮助开发人员在5分钟内转动电机
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