基于Xilinx FPGA的通用信号采集器
上一篇写了基于xilinx fpga的通用信号发生器的案例，反响比较好，很多朋友和我探讨相关的技术，其中就涉及到信号的采集，为了使该文更有血有肉，我在写一篇基于xilinx fpga的通用信号采集器，望能形成呼应，以解答大家的疑问。目的：1.通过设计实现信号采集与分析，掌握组合逻辑设计方法；2.通过设计实现信号的采集与分析，掌握信号采集原理。原理：利用fpga芯片，用verilog语言编写逻辑，控制ad0809进行ad转换。ad0809是带有8位ad转换器、8路多路开关以及微处理机兼容的控制逻辑的cmos组件，它是逐次逼近式的ad转换器。ad0809的内部结构图如下：
由上图可知，多路开关可选通8 个模拟通道，允许8路模拟量分时输入，共用ad转换器进行转换，三态输出锁存器用于锁存ad转换完成后的数字量，当oe为高时才可以从锁存器取出转换后的数据。通道选择如下图所示：
start为转换启动信号。当start上跳沿时，所有内部寄存器清零；下跳沿时，开始进行a/d 转换；在转换期间，start应保持低电平。eoc 为转换结束信号。当eoc 为高电平时，表明转换结束；否则，表明正在进行a/d 转换。oe为输出允许信号，用于控制三条输出锁存器向单片机输出转换得到的数据。oe＝1，输出转换得到的数据；oe＝0，输出数据线呈高阻状态。时序如下图所示：
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254源代码1.verilog源代码，datacollect.vmodule datacollect(sysclk, rst, adda, addb, addc, start, oe, datain, led_sel, led_seg);input sysclk, rst;input wire [7:0] datain;output reg adda, addb, addc, start, oe;output reg[3:0] led_sel;output reg[7:0] led_seg;reg [3:0] counter1;reg [7:0] readdata;reg [9:0] counter2;reg [15:0] sum;reg [7:0] averdata;reg [7:0] temp;reg [3:0] dataout1, dataout2, dataout3;reg [3:0] counter3;parameter zero = 8'b11111100,one = 8'b01100000, two = 8'b11011010;parameter three = 8'b11110010, four =8'b01100110;parameter five = 8'b10110110, six = 8'b10111110, seven =8'b11100000;parameter eight = 8'b11111110, nine = 8'b11110110, blank = 8'b00000000;always @(posedge sysclk or negedge rst)beginif (!rst)beginadda = 0;addb = 0;addc = 0;oe = 1;counter1 = 0;endelsebegincounter1 = counter1 + 1;case (counter1)3 : start = 0;4 : start = 1;5 : start = 0;10 : readdata = datain;15 : counter1 = 0;default : counter1 = counter1;endcaseendendalways @(posedge sysclk or negedge rst)beginif (!rst)begincounter2 = 0;sum = 0;averdata = 0;endelsebegincounter2 = counter2 + 1;if ((counter2%16) == 0)sum = sum + readdata;else if (counter2 > 512)beginaverdata = sum / 32;sum = 0;counter2 = 0;endendendalways @(averdata)begintemp = averdata;if (temp > 199)dataout3 = 2;else if (temp > 99)dataout3 = 1;elsedataout3 = 0;temp = temp - dataout3 * 100;if (temp > 89)dataout2 = 9;else if (temp > 79)dataout2 = 8;else if (temp > 69)dataout2 = 7;else if (temp > 59)dataout2 = 6;else if (temp > 49)dataout2 = 5;else if (temp > 39)dataout2 = 4;else if (temp > 29)dataout2 = 3;else if (temp > 19)dataout2 = 2;else if (temp > 9)dataout2 = 1;elsedataout2 = 0;temp = temp - dataout2 * 10;dataout1 = temp;if ((dataout3==0) && (dataout2==0))begindataout3 = 10;dataout2 = 10;endelse if (dataout3 == 0)dataout3 = 10;elsedataout3 = dataout3;endalways @(posedge sysclk or negedge rst)beginif (!rst)begincounter3 = 0;led_sel = 4'b0001; endelsebeginif (counter3 == 4)begincounter3 = 0;if (led_sel == 4'b1000)led_sel = 4'b0001;elseled_sel = led_sel << 1;endcounter3 = counter3 + 1;endendalways @(led_sel, dataout1, dataout2, dataout3)begincase (led_sel)4'b0001 :begincase (dataout1)0 : led_seg = zero;1 : led_seg = one;2 : led_seg = two;3 : led_seg = three;4 : led_seg = four;5 : led_seg = five;6 : led_seg = six;7 : led_seg = seven;8 : led_seg = eight;9 : led_seg = nine;default : led_seg = blank;endcaseend4'b0010 :begincase (dataout2)0 : led_seg = zero;1 : led_seg = one;2 : led_seg = two;3 : led_seg = three;4 : led_seg = four;5 : led_seg = five;6 : led_seg = six;7 : led_seg = seven;8 : led_seg = eight;9 : led_seg = nine;default : led_seg = blank;endcaseend4'b0100 :begincase (dataout3)0 : led_seg = zero;1 : led_seg = one;2 : led_seg = two;3 : led_seg = three;4 : led_seg = four;5 : led_seg = five;6 : led_seg = six;7 : led_seg = seven;8 : led_seg = eight;9 : led_seg = nine;default : led_seg = blank;endcaseend4'b1000 :begincase (10)0 : led_seg = zero;1 : led_seg = one;2 : led_seg = two;3 : led_seg = three;4 : led_seg = four;5 : led_seg = five;6 : led_seg = six;7 : led_seg = seven;8 : led_seg = eight;9 : led_seg = nine;default : led_seg = blank;endcaseenddefault :beginled_seg = 1'hx;endendcaseendendmodule2.引脚分配源代码，datacollect.ucfnet sysclk loc = p80;net rst loc = p57;net adda loc = p14;net addb loc = p16;net addc loc = p18;net oe loc = p23;net start loc = p27;net datain loc = p30;net datain loc = p33;net datain loc = p35;net datain loc = p37;net datain loc = p42;net datain loc = p44;net datain loc = p46;net datain loc = p48;net led_sel loc = p3;net led_sel loc = p5;net led_sel loc = p7;net led_sel loc = p9;net led_seg loc = p206;net led_seg loc = p204;net led_seg loc = p202;net led_seg loc = p200;net led_seg loc = p195;net led_seg loc = p193;net led_seg loc = p191;net led_seg loc = p187;ok了，可以使用了，按照为器件分配的引脚进行连线，系统时钟输入连1kmhz，可以旋转电位器以改变输入电压,此时可观察到数据管上数据变化。fpga，融入其中，乐趣无穷。。。。
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由上图可知，多路开关可选通8 个模拟通道，允许8路模拟量分时输入，共用ad转换器进行转换，三态输出锁存器用于锁存ad转换完成后的数字量，当oe为高时才可以从锁存器取出转换后的数据。通道选择如下图所示：
start为转换启动信号。当start上跳沿时，所有内部寄存器清零；下跳沿时，开始进行a/d 转换；在转换期间，start应保持低电平。eoc 为转换结束信号。当eoc 为高电平时，表明转换结束；否则，表明正在进行a/d 转换。oe为输出允许信号，用于控制三条输出锁存器向单片机输出转换得到的数据。oe＝1，输出转换得到的数据；oe＝0，输出数据线呈高阻状态。时序如下图所示：
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254源代码1.verilog源代码，datacollect.vmodule datacollect(sysclk, rst, adda, addb, addc, start, oe, datain, led_sel, led_seg);input sysclk, rst;input wire [7:0] datain;output reg adda, addb, addc, start, oe;output reg[3:0] led_sel;output reg[7:0] led_seg;reg [3:0] counter1;reg [7:0] readdata;reg [9:0] counter2;reg [15:0] sum;reg [7:0] averdata;reg [7:0] temp;reg [3:0] dataout1, dataout2, dataout3;reg [3:0] counter3;parameter zero = 8'b11111100,one = 8'b01100000, two = 8'b11011010;parameter three = 8'b11110010, four =8'b01100110;parameter five = 8'b10110110, six = 8'b10111110, seven =8'b11100000;parameter eight = 8'b11111110, nine = 8'b11110110, blank = 8'b00000000;always @(posedge sysclk or negedge rst)beginif (!rst)beginadda = 0;addb = 0;addc = 0;oe = 1;counter1 = 0;endelsebegincounter1 = counter1 + 1;case (counter1)3 : start = 0;4 : start = 1;5 : start = 0;10 : readdata = datain;15 : counter1 = 0;default : counter1 = counter1;endcaseendendalways @(posedge sysclk or negedge rst)beginif (!rst)begincounter2 = 0;sum = 0;averdata = 0;endelsebegincounter2 = counter2 + 1;if ((counter2%16) == 0)sum = sum + readdata;else if (counter2 > 512)beginaverdata = sum / 32;sum = 0;counter2 = 0;endendendalways @(averdata)begintemp = averdata;if (temp > 199)dataout3 = 2;else if (temp > 99)dataout3 = 1;elsedataout3 = 0;temp = temp - dataout3 * 100;if (temp > 89)dataout2 = 9;else if (temp > 79)dataout2 = 8;else if (temp > 69)dataout2 = 7;else if (temp > 59)dataout2 = 6;else if (temp > 49)dataout2 = 5;else if (temp > 39)dataout2 = 4;else if (temp > 29)dataout2 = 3;else if (temp > 19)dataout2 = 2;else if (temp > 9)dataout2 = 1;elsedataout2 = 0;temp = temp - dataout2 * 10;dataout1 = temp;if ((dataout3==0) && (dataout2==0))begindataout3 = 10;dataout2 = 10;endelse if (dataout3 == 0)dataout3 = 10;elsedataout3 = dataout3;endalways @(posedge sysclk or negedge rst)beginif (!rst)begincounter3 = 0;led_sel = 4'b0001; endelsebeginif (counter3 == 4)begincounter3 = 0;if (led_sel == 4'b1000)led_sel = 4'b0001;elseled_sel = led_sel << 1;endcounter3 = counter3 + 1;endendalways @(led_sel, dataout1, dataout2, dataout3)begincase (led_sel)4'b0001 :begincase (dataout1)0 : led_seg = zero;1 : led_seg = one;2 : led_seg = two;3 : led_seg = three;4 : led_seg = four;5 : led_seg = five;6 : led_seg = six;7 : led_seg = seven;8 : led_seg = eight;9 : led_seg = nine;default : led_seg = blank;endcaseend4'b0010 :begincase (dataout2)0 : led_seg = zero;1 : led_seg = one;2 : led_seg = two;3 : led_seg = three;4 : led_seg = four;5 : led_seg = five;6 : led_seg = six;7 : led_seg = seven;8 : led_seg = eight;9 : led_seg = nine;default : led_seg = blank;endcaseend4'b0100 :begincase (dataout3)0 : led_seg = zero;1 : led_seg = one;2 : led_seg = two;3 : led_seg = three;4 : led_seg = four;5 : led_seg = five;6 : led_seg = six;7 : led_seg = seven;8 : led_seg = eight;9 : led_seg = nine;default : led_seg = blank;endcaseend4'b1000 :begincase (10)0 : led_seg = zero;1 : led_seg = one;2 : led_seg = two;3 : led_seg = three;4 : led_seg = four;5 : led_seg = five;6 : led_seg = six;7 : led_seg = seven;8 : led_seg = eight;9 : led_seg = nine;default : led_seg = blank;endcaseenddefault :beginled_seg = 1'hx;endendcaseendendmodule2.引脚分配源代码，datacollect.ucfnet sysclk loc = p80;net rst loc = p57;net adda loc = p14;net addb loc = p16;net addc loc = p18;net oe loc = p23;net start loc = p27;net datain loc = p30;net datain loc = p33;net datain loc = p35;net datain loc = p37;net datain loc = p42;net datain loc = p44;net datain loc = p46;net datain loc = p48;net led_sel loc = p3;net led_sel loc = p5;net led_sel loc = p7;net led_sel loc = p9;net led_seg loc = p206;net led_seg loc = p204;net led_seg loc = p202;net led_seg loc = p200;net led_seg loc = p195;net led_seg loc = p193;net led_seg loc = p191;net led_seg loc = p187;ok了，可以使用了，按照为器件分配的引脚进行连线，系统时钟输入连1kmhz，可以旋转电位器以改变输入电压,此时可观察到数据管上数据变化。fpga，融入其中，乐趣无穷。。。。
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